Counters Questions

• A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
• The final output of a modulus-8 counter occurs one time for every ________.
• How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
• A 4-bit counter has a maximum modulus of ________.
• How many data bits can be stored in the register shown below?
• A seven-segment, common-anode LED display is designed for:
• An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
• Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:
• In an HDL ring counter, many invalid states are included in the programming by:
• List which pins need to be connected together on a 7493 to make a MOD-12 counter.
• A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.
• Integrated-circuit counter chips are used in numerous applications including:
• Which of the following is an invalid state in an 8421 BCD counter?
• A counter with a modulus of 16 acts as a ________.
• Four cascaded modulus-10 counters have an overall modulus of ________.
• Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
• What type of device is shown below?
• After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?
• A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?
• Three cascaded modulus-5 counters have an overall modulus of ________.