Divide-by-N by external gating — what action occurs at the predetermined terminal count? Any divide-by-N counter can be realized by adding external gating so that the counter will ________ when a chosen terminal count is reached.

Introduction / Context:
When a required modulus is not a power of two, designers commonly “truncate” a binary counter by externally detecting a terminal count and forcing the counter back to a known state. This technique is foundational for creating arbitrary divide-by-N frequency dividers and sequence generators using standard binary counters.

Given Data / Assumptions:

• Base counter is a binary up-counter.
• Combinational logic detects a particular output pattern (terminal count).
• On detection, a control input forces the counter to a known start state.

Concept / Approach:
To obtain an exact period of N clocks, detect the Nth state and assert the asynchronous clear (reset). The counter then immediately returns to 000… and begins counting the next cycle. Alternatively, for non-zero starting states, a synchronous/asynchronous load may be used, but the classic divide-by-N approach is to reset at the terminal count corresponding to N, yielding an output that repeats every N pulses.

Step-by-Step Solution:

Verification / Alternative check:
Compare with a 6-to-10 decoder used to create a divide-by-10 from a 4-bit binary counter: detecting 1010₂ (decimal 10) and resetting yields MOD-10 behavior (a decade counter).

Why Other Options Are Wrong:

• “HIGH” or “LOW”: logic levels, not actions.
• Preset: can implement a different start state but the textbook divide-by-N phrasing is to reset at N.
• Tri-state outputs: unrelated to modulus control.

Common Pitfalls:

• Failing to consider reset pulse width and propagation delay; ensure reset cleanly clears one count only.
• Glitchy decode can cause premature resets; use synchronous reset or registered decode if necessary.

Final Answer:
reset