Truly synchronous multistage counter requirement For a multistage counter to be genuinely synchronous (all stages update together), the ________ of each stage must be tied to ________.

Introduction / Context:
In synchronous counters, all flip-flops change state simultaneously on the same clock edge. This eliminates the ripple delays inherent in asynchronous counters and allows higher operating frequencies with predictable timing. The key design requirement is how the clock is distributed.

Given Data / Assumptions:

• Each stage is a clocked flip-flop (e.g., D, JK, or T) with a clock input Cp.
• Combinational logic may generate next-state signals, but should not create multiple, skewed clock domains.
• We want every stage to respond to the same clock edge.

Concept / Approach:
A truly synchronous counter feeds a common clock to every flip-flop (Cp pins tied to the same line). Next-state logic determines which stages toggle/set/reset, but the actual state update occurs concurrently on the global clock transition. By contrast, ripple counters route a prior stage's output into the next stage's clock, creating accumulated delay and skew.

Step-by-Step Solution:

Verification / Alternative check:
Timing simulation shows one uniform clock net and no multi-level clock chains. Hardware measurements reveal minimal skew between stage outputs at the active edge.

Why Other Options Are Wrong:

• CE to same clock line: CE (clock enable) is not the system clock; tying enables together does not ensure synchronous sampling if clocks differ.
• Terminal count or “both clock input lines”: Misapplies ripple techniques or introduces ambiguous clocking, defeating synchronous behavior.

Common Pitfalls:
Deriving per-stage clocks from logic signals (gated clocks) which add skew and glitch sensitivity; proper synchronous design uses a common clock and enables within data paths, not clock gating wherever possible.

Final Answer:
Cp, the same clock input line