Counters Questions

• For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
• A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.
• A ripple counter's speed is limited by the propagation delay of:
• In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.
• Synchronous binary counters can only be used for the application of timing of digital systems.
• To cascade is to connect in parallel.
• Shift register counters use logic functions to reset the registers when the desired count is reached.
• Once an up/down counter begins its count sequence, it cannot be reversed.
• An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.
• Bidirectional shift registers can shift data either right or left.
• Parallel in/parallel out registers have parallel input and output busses.
• A glitch is a short pulse resulting in an undesired result in a digital circuit.
• The term synchronous refers to events that do not occur at the same time.
• The modulus of a counter is the actual number of states in its sequence.
• All decade counters are BCD counters.
• In VHDL, when we want to remember a value it must be stored in a VARIABLE.
• The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
• A ripple counter is an asynchronous counter.
• Shift registers are used to store and transfer data.
• A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.