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General Knowledge
Verbal Reasoning
Computer Science
Interview
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Counters Questions
Counter ICs — 7490 vs. 7492 Modulus Identify the correct modulus (divide-by value) for each of these TTL counters: 7490 and 7492.
BCD-to-7-Segment Driver 7447 — Determine Outputs for Digit 9 Given a 7447 common-anode driver with inputs RBI = 0, LT = 1, and BCD A3 A2 A1 A0 = 1 0 0 1 (decimal 9), list the states of RBO and segments a–g (active-LOW outputs).
Number Systems — Convert 15,536 (Decimal) to Hexadecimal Find the hexadecimal equivalent of the decimal number 15,536, showing the place-value reasoning.
Cascaded Decade Counters — Overall Divide Ratio If three decade (MOD-10) counters are cascaded, by what factor is the input frequency divided at the final output?
Binary Counter — Terminal Count in DOWN Mode (3-Bit) For a 3-bit binary counter operating in DOWN mode, what is the terminal count (the state at which it rolls under to the maximum state)?
One-Shot in HDL — Make the Circuit Fire Once per Rising Edge In a hardware description language (HDL), which technique ensures a circuit responds once to each positive transition (rising edge) on a trigger input, implementing a one-shot behavior?
Asynchronous (Ripple) Counters — Key Limitation What is a major drawback of asynchronous (ripple) counters compared with synchronous counters for frequency-scaling applications?
Cascading counters — overall modulus calculation When two digital counters are cascaded (one drives the next), the overall MOD (modulus) of the combined counter is equal to the ________ of their individual MOD numbers.
Ripple counter timing — recycle delay through 4 cascaded flip-flops A 4-bit ripple counter uses flip-flops with 15 ns clock-to-Q propagation delay each. How long does it take to recycle from 1111 back to 0000 (worst-case total ripple time)?
Flip-flops needed for a decade (MOD-10) counter How many flip-flops are required to construct a decade counter that counts 0 through 9 and then recycles?
System fails to produce data output — flip-flops test OK individually A multistage sequential circuit produces no data output. Each flip-flop checks OK with a logic probe and pulser when tested individually. Which fault could still explain the system-level failure?
Designing synchronous nonbinary counters The process for creating a synchronous counter that counts in a nonbinary sequence (custom MOD) is primarily based on:
Retriggerable edge-triggered one-shot in VHDL — impossible condition at the clock edge In a retriggerable, edge-triggered one-shot described in VHDL using a counter, which of the following conditions will
not
exist at a clock edge?
Correct start-up for a ring counter To ensure correct operation at power-up, starting a ring counter requires:
Shift-register counter types — identification Which of the following is a type of shift-register-based counter?
Master Reset (MR) on 4-bit binary counters — behavior and usage Select the statement that best describes how the Master Reset inputs (MR1 and MR2) work on typical 4-bit binary counters (e.g., TTL/CMOS families).
Ripple (asynchronous) MOD-16 counter — output frequencies per stage A 22 MHz clock drives a MOD-16 binary ripple counter (4 cascaded divide-by-2 stages). What are the output frequencies Q1 through Q4?
Modulus understanding — output repetition rate For a modulus-8 (MOD-8) counter, the final output pattern repeats how often relative to the input clock pulses?
Complete state decoding for a MOD-64 counter — gate count and inputs How many AND gates are required to decode every state of a MOD-64 counter, and how many inputs must each AND gate have?
4-bit counter capacity — maximum modulus A binary counter built from 4 flip-flops has what maximum modulus (number of unique states before repeating)?
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