Curioustab

Home » Electronics » Sequential Logic Circuits

When the output of a tri-state shift register is disabled, the output level is placed in a:

float state
LOW state
high impedance state
float state and a high impedance state

Correct Answer: float state and a high impedance state

← Previous Question Next Question→

More Questions from Sequential Logic Circuits

A comparison between ring and johnson counters indicates that:
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
One of the major drawbacks to the use of asynchronous counters is that:
What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
To operate correctly, starting a ring counter requires:
A ripple counter's speed is limited by the propagation delay of:
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
What is a shift register that will accept a parallel input and can shift data left or right called?
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Which type of device may be used to interface a parallel data format with external equipment's serial format?

Discussion & Comments

No comments yet. Be the first to comment!

Join Discussion