Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:
Flip-flops possess two categories of control: synchronous inputs, sampled at the active clock edge, and asynchronous inputs (such as direct preset/set and direct clear/reset), which override normal clocked operation. Understanding which signals ignore the clock is vital for power-on initialization and robust state machines.
Given Data / Assumptions:
Concept / Approach:
Asynchronous inputs bypass the synchronous data path and act directly on the storage nodes. Therefore, when an asynchronous preset or clear is asserted, the output changes immediately (subject to propagation delay) without waiting for a clock edge. Designers use this for deterministic startup (e.g., clearing state registers at reset) and for emergency overrides.
Step-by-Step Solution:
Verification / Alternative check:
Datasheets specify separate asynchronous set/reset timing parameters (t_preset, t_clear) distinct from setup/hold to the clocked inputs; simulation and bench tests show immediate effect when these pins toggle.
Why Other Options Are Wrong:
Common Pitfalls:
Driving asynchronous inputs with noisy signals; failing to release reset synchronously (which can cause domain crossing issues); assuming preset/clear obey normal setup/hold to the clock.
Final Answer:
Correct
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