Asynchronous (ripple) counters — clocking method clarified: In an asynchronous counter, do all flip-flops (i.e., each state transition) receive the same clock pulse simultaneously, or does the clock ripple from one stage to the next? Choose the correct characterization of how states are clocked.

Introduction / Context:
Digital counters are built from cascaded flip-flops and are categorized by how those flip-flops receive clock transitions. This question probes whether an asynchronous (ripple) counter clocks every flip-flop from the same external clock, or whether the clock edge ripples stage-to-stage, which affects speed, timing skew, and maximum operating frequency.

Given Data / Assumptions:

• The term “asynchronous counter” is synonymous with “ripple counter.”
• Each flip-flop toggles on the appropriate transition (often falling edge) of its clock input.
• Propagation delays through flip-flops are non-zero and accumulate.

Concept / Approach:
In an asynchronous counter, the first flip-flop is driven by the external clock. Each subsequent flip-flop uses the output of the previous stage as its clock. Thus, clock information propagates serially—ripple fashion—rather than being applied to all stages simultaneously. Because the stages do not switch at exactly the same time, temporary decoding glitches and a lower maximum count rate are typical compared to synchronous designs where a common clock edge reaches all stages together.

Step-by-Step Solution:

Verification / Alternative check:
Timing diagrams show Q0 toggling first; then, slightly later (by t_pd), Q1 toggles, and so on. The chain of delays confirms the ripple mechanism rather than simultaneous clocking.

Why Other Options Are Wrong:

• Correct: Not applicable; asynchronous counters do not share one global simultaneous clock edge.
• Valid only for mod-2 counters: Even mod-2 ripple counters still ripple (though with one stage).
• Applies to synchronous counters only: Yes, simultaneous clocking characterizes synchronous counters, not asynchronous.
• Depends on propagation delay being zero: Real t_pd is never zero; ripple behavior remains fundamental.

Common Pitfalls:
Confusing “asynchronous” with “no clock”; assuming all counters share the same clock topology; overlooking hazards from accumulated propagation delays when decoding states.

Final Answer:
Incorrect