Q: Shift-register behavior — Which register type accepts a serial input bit-by-bit and outputs the stored data serially one bit at a time (i.e., serial in, serial out)?

Introduction: Shift registers are used to convert between serial and parallel formats and to delay or manipulate bit streams. Identifying the correct register type is crucial for interfacing ICs and communication links. Given Data / Assumptions: Input arrives one bit per clock. Output is also one bit per clock. No parallel load or read is required for the main function described. Concept / Approach: Register acronyms specify data flow: PIPO (parallel in, parallel out), SISO (serial in, serial out), SIPO (serial in, parallel out), PISO (parallel in, serial out). The described behavior matches SISO, often used as a simple delay line or pipeline of bits. Step-by-Step Solution: Accept serial input at the first flip-flop each clock.Shift existing bits one stage along per clock.Read the last stage as serial output each clock.This behavior defines a SISO shift register. Verification / Alternative check: Timing diagrams show a one-clock per stage latency from input to output, consistent with serial-in, serial-out operation used for digital delay lines. Why Other Options Are Wrong: PIPO: No serial behavior; both input and output are parallel. SIPO: Serial input but parallel output. PISO: Parallel input but serial output. Bi-directional universal: Supports many modes; not uniquely SISO. Common Pitfalls: Confusing SISO with SIPO/PISO during interface design. Ignoring required clocking and setup/hold constraints for reliable shifting. Final Answer: SISO

Q: Ring counter initialization — For correct operation at startup, how should a ring counter be initialized?

Introduction: Ring counters circulate a single 1 (or 0) through a chain of flip-flops to create equally spaced timing phases. Proper initialization ensures that exactly one active bit exists; otherwise, the sequence is invalid or ambiguous. Given Data / Assumptions: N flip-flops connected in a loop (Q of last feeds the first). Desire is a 1-hot sequence for decoding simple timing signals. Flip-flops support preset and clear controls. Concept / Approach: To obtain a 1-hot pattern, set exactly one flip-flop to 1 and all others to 0 at startup. Each clock then rotates the 1 to the next stage, delivering predictable timing pulses with no overlaps or gaps. Step-by-Step Solution: Apply asynchronous preset to one chosen flip-flop (set = 1).Apply asynchronous clear to all remaining flip-flops (set = 0).Release controls; on each clock, the single 1 shifts to the next stage.Sequence remains valid and cyclic with period equal to the number of stages. Verification / Alternative check: Waveforms demonstrate a rotating single 1 across outputs Q0, Q1, …, QN-1. Any other initialization (e.g., all zeros or multiple ones) either stalls the ring or produces multiple pulses per cycle. Why Other Options Are Wrong: Clearing all / presetting all: Produces all-0 or all-1 states, not 1-hot. Clearing one, presetting others: Creates (N−1) ones, breaking 1-hot operation. No initialization: Startup state is unknown; sequence may be invalid. Common Pitfalls: Relying on power-up defaults; many flip-flops power up unpredictably. Neglecting metastability or asynchronous control release skew. Final Answer: presetting one flip-flop and clearing all the others

Q: Ripple counter speed — The maximum counting speed of a ripple counter is limited primarily by the propagation delay of which elements?

Introduction: Ripple (asynchronous) counters propagate toggles from one stage to the next, so their speed is constrained by cumulative delays. Identifying the limiting element helps estimate maximum clock rates and choose suitable architectures. Given Data / Assumptions: N flip-flop stages, cascaded in ripple fashion. Nonzero propagation delay for each flip-flop (t_pd). Negligible extra logic between stages for the basic counter. Concept / Approach: The worst-case settling time after a clock edge is approximately the sum of flip-flop delays along the ripple path. Thus, each flip-flop’s delay contributes directly to the maximum frequency limit. External gates may affect decoded outputs, but the inherent limit comes from the flip-flops themselves in the counting chain. Step-by-Step Solution: Let t_pd(ff) be per-stage delay.Total worst-case ripple ≈ N * t_pd(ff).Require next clock period > N * t_pd(ff) for correct operation.Hence, speed is limited by each flip-flop’s delay accumulating through stages. Verification / Alternative check: Datasheets for ripple counters specify maximum toggle frequency decreasing as bit-width increases, reflecting cumulative flip-flop delays rather than external gate delays. Why Other Options Are Wrong: All flip-flops and gates / flip-flops with gates / only gates: Gates impact decoded outputs but not the fundamental counting path delay in the simplest ripple counter. Clock source only: Clock quality matters, but does not set the internal combinational delay limit. Common Pitfalls: Using asynchronous decoded outputs without registering; glitches may be captured. Ignoring temperature and supply variation that increases t_pd at extremes. Final Answer: each flip-flop

Question 1

In digital timekeeping applications, which systems most commonly employ mod-6 and mod-12 counters for dividing and displaying time?

Accepted Answer

Introduction / Context: Time displays rely on dividing a reference frequency into human-readable units. Modulus counters (counters that reset after reaching a fixed count) are arranged to implement decimal or sexagesimal divisions. Mod-6 and mod-12 counters are classic building blocks for hours and seconds/minutes displays in clocks. Given Data / Assumptions: Seconds and minutes are base-60 (6×10) systems. Hours are often displayed in 12-hour format. Counters receive a known clock (e.g., 1 Hz derived from a crystal). Concept / Approach: A mod-10 counter cycles 0–9; cascading a mod-6 and a mod-10 yields 0–59 for seconds/minutes. For hours, a mod-12 counter cycles 1–12 (often implemented as 0–11 then converted). These modulus values map neatly onto the conventional time base used by digital clocks, and decoder/driver circuits feed seven-segment displays. Step-by-Step Solution: Derive 1 Hz from a crystal (e.g., 32.768 kHz divided by 2^15).Use mod-10 for units of seconds and a following mod-6 for tens of seconds to reach 60 states.Repeat the mod-6/mod-10 pair for minutes.Use a mod-12 counter to track hours in 12-hour format, with AM/PM toggle. Verification / Alternative check: Common digital clock ICs and reference designs show exactly these division chains, confirming the prevalence of mod-6 and mod-12 counters in clock applications. Why Other Options Are Wrong: Frequency counters: Typically use binary or decade counters but not specifically mod-6 and mod-12 combinations. Multiplexed displays: A display driving technique, not a counting modulus choice. Power meters / PWM: Use different counting/control strategies unrelated to 12- or 60-based time divisions. Common Pitfalls: Mistaking mod-60 as a single counter; it is usually realized by mod-6 and mod-10 cascades. Forgetting display decoding for leading zero suppression or 12→1..12 mapping. Final Answer: digital clocks

Question 2

In tri-state (three-state) logic, when the output of a shift register is disabled, into what electrical condition is its output placed?

Accepted Answer

Introduction / Context: Tri-state outputs allow multiple devices to share a common bus. Besides logic 0 and logic 1, a third state disconnects the output driver so that it neither sources nor sinks bus current. Recognizing this state is critical for avoiding bus contention when several devices might otherwise drive the same line. Given Data / Assumptions: A shift register with an enable (OE) or output control pin. Bus-oriented design where only one device should drive the line at a time. Disabled output should not affect bus level. Concept / Approach: The disabled or tri-stated condition is called the high-impedance (Hi-Z) state. In Hi-Z, the output behaves electrically like an open circuit, effectively removing the device from the bus. This permits another enabled device to drive the line without conflict, and also allows external pull-ups/pull-downs to set the idle level. Step-by-Step Solution: Assert OE so that the output drivers turn off.Measure bus current contribution: It becomes negligible (no active drive).Observe that bus level is determined by the enabled driver or bias resistors.Therefore, the output is in a high-impedance state. Verification / Alternative check: Datasheets specify output leakage currents (e.g., ±10 µA) in Hi-Z, confirming near-open-circuit behavior. Timing diagrams also show OE controlling transitions into and out of Hi-Z to prevent overlap driving. Why Other Options Are Wrong: LOW or intermediate bias: These imply the device is still driving; not true for Hi-Z. Float state: Informally used, but the precise engineering term is high impedance; floating is a symptom, not the defined output mode. Float + Hi-Z: Redundant/confusing; the canonical term is Hi-Z. Common Pitfalls: Leaving a bus with all drivers tri-stated and no bias resistors, causing undefined levels and noise susceptibility. Enabling more than one driver simultaneously, leading to destructive contention currents. Final Answer: high impedance state

Question 3

Considering ring counters versus Johnson (twisted-ring) counters, which statement correctly identifies a key structural difference between them?

Accepted Answer

Introduction / Context: Ring and Johnson counters are shift-register based counters used for sequence generation and timing. While both circulate patterns through flip-flops, the way feedback is applied differentiates their state counts and decoding requirements. Recognizing the feedback type helps in choosing the right counter for a given number of states and ease of decoding. Given Data / Assumptions: Ring counter: circulates a single 1 (one-hot) through N flip-flops. Johnson counter: feeds back the inverted output of the last flip-flop to the first. Both are clocked shift registers. Concept / Approach: A ring counter with N flip-flops provides N distinct one-hot states and generally needs minimal decoding but uses many flip-flops to get many states. A Johnson counter (twisted ring) with N flip-flops produces 2N unique states because the inverted feedback generates a two-phase pattern sequence. This can reduce decoding complexity for certain sequences and is the hallmark trait: inverted feedback path from the last stage to the first. Step-by-Step Solution: Ring: Q pattern 1000 → 0100 → 0010 → 0001 → 1000 (no inversion).Johnson: Q pattern evolves as 1111 → 1110 → ... → 0000 → 0001 → ... (due to inverted feedback).Count of states: Ring = N; Johnson = 2N.Conclusion: Johnson uses inverted feedback. Verification / Alternative check: Textbook timing diagrams and simulations show the twisted feedback for Johnson counters and the doubled state count relative to a simple ring, confirming the structural difference. Why Other Options Are Wrong: Ring has inverted feedback: Incorrect; that defines Johnson, not ring. Flip-flop counts: Johnson achieves more states with the same flip-flops, not more flip-flops. Identical feedback: Contradicts the core distinction between the two. Common Pitfalls: Confusing the one-hot nature of ring counters with Johnson sequences that feature consecutive ones and zeros. Assuming both have the same number of states per flip-flop; Johnson doubles the state count. Final Answer: a johnson counter has an inverted feedback path

Question 4

Asynchronous binary down counter — On each active clock pulse, what happens to the parallel output word (i.e., the binary count present across all flip-flop outputs) of an asynchronous DOWN counter?

Accepted Answer

Introduction: An asynchronous (ripple) down counter is a fundamental digital circuit used to count downward in binary. Understanding how the parallel output word changes with each clock pulse is essential for timing, division, and event counting applications. Given Data / Assumptions: The counter is configured as a binary DOWN counter. Flip-flops are arranged in ripple fashion (output of one feeds the clock of the next). Each valid clock pulse triggers one count event. No asynchronous clears/loads occur during counting. Concept / Approach: In a down counter, the least significant bit toggles every clock, and higher bits toggle on the appropriate transitions of lower bits. Regardless of internal propagation delays, the ideal net effect per external clock event is that the overall binary number represented by the parallel outputs steps down by one count (modulo the counter length). Step-by-Step Solution: Model the N-bit count at time k as Q(k).On the next eligible clock edge, the count becomes Q(k+1) = Q(k) − 1 (mod 2^N) for a down counter.Internal ripple may cause brief intermediate states, but the final settled state is one less than the previous.Therefore, the parallel output word decreases by exactly one count per clock. Verification / Alternative check: Simulate a 4-bit ripple down counter: 0000 underflows to 1111, then 1110, 1101,… Each clock decrements the binary value by one, confirming the rule independently of transient glitches. Why Other Options Are Wrong: Decreases by 2: That would require two toggles per clock or a different modulus. Increases by 1/2: Describes up counting, not down counting. Toggles randomly: Ripple propagation causes momentary glitches, not random final values. Common Pitfalls: Observing intermediate ripple states and misinterpreting them as final counts. Forgetting modulus wraparound at 000…0. Final Answer: The output word decreases by 1.

Question 5

Asynchronous (ripple) counters — What major limitation affects their use at high frequencies?

Accepted Answer

Introduction: Ripple counters are simple and hardware-efficient, but their stage-to-stage triggering creates timing skew. Recognizing this limitation helps you decide when to choose synchronous counters instead. Given Data / Assumptions: Asynchronous counter with cascaded flip-flops (output of one is clock for the next). Non-zero propagation delay for each flip-flop. Interest is in maximum reliable counting frequency. Concept / Approach: Because each stage toggles after the previous one, total response time accumulates roughly as the sum of propagation delays through multiple stages. At high input clock rates, the outputs may not settle before the next clock edge, causing miscounts or decoding errors. Step-by-Step Solution: Let t_pd be propagation delay per flip-flop.Worst-case count ripple traverses N stages → cumulative delay ≈ N * t_pd.Maximum usable clock frequency f_max is limited so that the next clock arrives after outputs have settled: f_max < 1 / (N * t_pd).Thus, higher frequencies are limited by propagation delays. Verification / Alternative check: Timing diagrams show glitch windows during ripple transitions. Synchronous designs eliminate these by clocking all stages together, supporting much higher f_max. Why Other Options Are Wrong: Low-frequency limitation: Delays are negligible at low frequency. No drawbacks / no delays: Physically inaccurate; every device has finite delay. Voltage-only limitation: Speed is fundamentally timing-limited, not just supply-limited. Common Pitfalls: Decoding ripple outputs without registering them, which can capture transient states. Underestimating worst-case t_pd across PVT (process, voltage, temperature). Final Answer: high-frequency applications are limited because of internal propagation delays

Question 6

Shift-register behavior — Which register type accepts a serial input bit-by-bit and outputs the stored data serially one bit at a time (i.e., serial in, serial out)?

Accepted Answer

Introduction: Shift registers are used to convert between serial and parallel formats and to delay or manipulate bit streams. Identifying the correct register type is crucial for interfacing ICs and communication links. Given Data / Assumptions: Input arrives one bit per clock. Output is also one bit per clock. No parallel load or read is required for the main function described. Concept / Approach: Register acronyms specify data flow: PIPO (parallel in, parallel out), SISO (serial in, serial out), SIPO (serial in, parallel out), PISO (parallel in, serial out). The described behavior matches SISO, often used as a simple delay line or pipeline of bits. Step-by-Step Solution: Accept serial input at the first flip-flop each clock.Shift existing bits one stage along per clock.Read the last stage as serial output each clock.This behavior defines a SISO shift register. Verification / Alternative check: Timing diagrams show a one-clock per stage latency from input to output, consistent with serial-in, serial-out operation used for digital delay lines. Why Other Options Are Wrong: PIPO: No serial behavior; both input and output are parallel. SIPO: Serial input but parallel output. PISO: Parallel input but serial output. Bi-directional universal: Supports many modes; not uniquely SISO. Common Pitfalls: Confusing SISO with SIPO/PISO during interface design. Ignoring required clocking and setup/hold constraints for reliable shifting. Final Answer: SISO

Question 7

Ring counter initialization — For correct operation at startup, how should a ring counter be initialized?

Accepted Answer

Introduction: Ring counters circulate a single 1 (or 0) through a chain of flip-flops to create equally spaced timing phases. Proper initialization ensures that exactly one active bit exists; otherwise, the sequence is invalid or ambiguous. Given Data / Assumptions: N flip-flops connected in a loop (Q of last feeds the first). Desire is a 1-hot sequence for decoding simple timing signals. Flip-flops support preset and clear controls. Concept / Approach: To obtain a 1-hot pattern, set exactly one flip-flop to 1 and all others to 0 at startup. Each clock then rotates the 1 to the next stage, delivering predictable timing pulses with no overlaps or gaps. Step-by-Step Solution: Apply asynchronous preset to one chosen flip-flop (set = 1).Apply asynchronous clear to all remaining flip-flops (set = 0).Release controls; on each clock, the single 1 shifts to the next stage.Sequence remains valid and cyclic with period equal to the number of stages. Verification / Alternative check: Waveforms demonstrate a rotating single 1 across outputs Q0, Q1, …, QN-1. Any other initialization (e.g., all zeros or multiple ones) either stalls the ring or produces multiple pulses per cycle. Why Other Options Are Wrong: Clearing all / presetting all: Produces all-0 or all-1 states, not 1-hot. Clearing one, presetting others: Creates (N−1) ones, breaking 1-hot operation. No initialization: Startup state is unknown; sequence may be invalid. Common Pitfalls: Relying on power-up defaults; many flip-flops power up unpredictably. Neglecting metastability or asynchronous control release skew. Final Answer: presetting one flip-flop and clearing all the others

Question 8

Ripple counter speed — The maximum counting speed of a ripple counter is limited primarily by the propagation delay of which elements?

Accepted Answer

Introduction: Ripple (asynchronous) counters propagate toggles from one stage to the next, so their speed is constrained by cumulative delays. Identifying the limiting element helps estimate maximum clock rates and choose suitable architectures. Given Data / Assumptions: N flip-flop stages, cascaded in ripple fashion. Nonzero propagation delay for each flip-flop (t_pd). Negligible extra logic between stages for the basic counter. Concept / Approach: The worst-case settling time after a clock edge is approximately the sum of flip-flop delays along the ripple path. Thus, each flip-flop’s delay contributes directly to the maximum frequency limit. External gates may affect decoded outputs, but the inherent limit comes from the flip-flops themselves in the counting chain. Step-by-Step Solution: Let t_pd(ff) be per-stage delay.Total worst-case ripple ≈ N * t_pd(ff).Require next clock period > N * t_pd(ff) for correct operation.Hence, speed is limited by each flip-flop’s delay accumulating through stages. Verification / Alternative check: Datasheets for ripple counters specify maximum toggle frequency decreasing as bit-width increases, reflecting cumulative flip-flop delays rather than external gate delays. Why Other Options Are Wrong: All flip-flops and gates / flip-flops with gates / only gates: Gates impact decoded outputs but not the fundamental counting path delay in the simplest ripple counter. Clock source only: Clock quality matters, but does not set the internal combinational delay limit. Common Pitfalls: Using asynchronous decoded outputs without registering; glitches may be captured. Ignoring temperature and supply variation that increases t_pd at extremes. Final Answer: each flip-flop

Question 9

Generating equally spaced timing pulses — Which counter/sequencer topology is commonly used to create a sequence of evenly spaced timing outputs with simple decoding?

Accepted Answer

Introduction: Timing generators often need multiple nonoverlapping, evenly spaced phase signals. Certain counter topologies simplify decoding and ensure uniform spacing without complex logic. Given Data / Assumptions: Goal: produce a set of sequential timing pulses, one per clock step. Low logic complexity desired for decoding. Consistent duty cycle and spacing preferred. Concept / Approach: A Johnson counter (twisted ring) feeds the inverted output of the last flip-flop back to the first. It cycles through 2N unique states using N flip-flops, providing evenly spaced, easily decoded outputs. Simple gating can extract narrow pulses or phase signals with minimal logic compared to binary counters. Step-by-Step Solution: Construct N-stage Johnson counter with feedback from inverted last stage.As the sequence advances, a pattern of consecutive ones and zeros rotates.Decode transitions with simple AND/OR gating to produce one-hot timing pulses.Result: equally spaced pulses over a 2N-step cycle. Verification / Alternative check: Design texts show that, for the same number of flip-flops, Johnson counters need fewer gates to obtain nonoverlapping phases than binary counters, and are widely used in timing sequencers and DAC timing logic. Why Other Options Are Wrong: Shift register sequencer / ring: Workable, but Johnson offers 2N states and easier decoding for equal spacing. Binary: Requires more complex decoding to obtain equal spacing and one-hot pulses. Clock: A clock alone is a single pulse train, not a sequencer topology. Common Pitfalls: Mistaking simple ring for Johnson; the twisted feedback differentiates them. Ignoring reset/initialization to a valid Johnson state. Final Answer: johnson

Question 10

Universal shift register — What do you call a shift register that accepts a parallel load and can shift data either left or right?

Accepted Answer

Introduction: Many applications require both parallel interfacing and directional shifting for alignment, serialization, or arithmetic. The device that provides all these capabilities is commonly known as a universal shift register. Given Data / Assumptions: Parallel loading needed for fast initialization or bus transfers. Ability to shift left or right on command. Standard control inputs for mode selection. Concept / Approach: A universal shift register supports four primary modes: hold (no change), shift left, shift right, and parallel load. Because it can shift in both directions and accept a parallel word, it is termed a bidirectional universal shift register. Typical IC examples are the 74x194/195 families. Step-by-Step Solution: Provide control lines to select among hold, shift-left, shift-right, and parallel-load modes.For parallel load, data on D inputs is clocked into all stages simultaneously.For shifting, serial inputs at either end inject new bits while existing bits move accordingly.Outputs present the updated word or serial bit depending on usage. Verification / Alternative check: Datasheets name these parts “universal” exactly because they combine bidirectional shifting with parallel loading, unlike simpler SIPO or PISO devices that lack at least one capability. Why Other Options Are Wrong: Tri-state: Refers to output enable behavior, not shifting modes. End around: Describes feedback to form ring/Johnson counters, not general loading/shifting. Conversion: Vague; does not denote register capabilities. SIPO/SISO hybrid without parallel load: Lacks the required parallel loading feature. Common Pitfalls: Confusing parallel load with synchronous set/reset; load replaces the entire word. Neglecting direction control setup/hold timing before the clock edge. Final Answer: bidirectional universal

Question 11

Synchronous vs. ripple counters — Why do synchronous counters avoid the delay issues found in asynchronous (ripple) counters?

Accepted Answer

Introduction: Synchronous counters are preferred for high-speed designs because they eliminate ripple-through timing uncertainty. Understanding the mechanism behind this improvement is critical for robust digital timing design. Given Data / Assumptions: All counter stages share a common clock in synchronous designs. Next-state logic for each stage is precomputed before the clock edge. Flip-flops have matched (bounded) clock-to-Q timing. Concept / Approach: When all flip-flops are clocked together, state transitions occur concurrently rather than rippling from stage to stage. The only relevant timing is the clock-to-Q of the flip-flops plus the propagation through the next-state combinational logic, not the sum of many cascaded FF delays. Step-by-Step Solution: Provide a global clock to every flip-flop.Compute each D (or T/J/K) input from present state using combinational logic.On the next clock edge, all stages update simultaneously.Glitches in intermediate logic are not latched if setup/hold are respected. Verification / Alternative check: Timing analysis for synchronous counters uses a single clock domain with clear setup/hold constraints, unlike ripple chains that have multiple derived clocks and skew, explaining the higher maximum frequency achievable. Why Other Options Are Wrong: Only first/last or only last stage clocking: Still creates ripple paths. No clock usage: Counters are sequential and require a clock. Analog timing: Irrelevant; counters are purely digital sequential circuits. Common Pitfalls: Failing to distribute a low-skew clock; excessive skew reintroduces hazards. Ignoring worst-case path delays in next-state logic, which set clock period limits. Final Answer: input clock pulses are applied simultaneously to each stage

Question 12

Parallel–serial interfacing — Which device is typically used to bridge a microprocessor’s parallel data bus to an external serial communications format?

Accepted Answer

Introduction: Systems often need to communicate over serial links (e.g., RS-232, RS-485, UART-over-USB) while the CPU presents data on a parallel bus. A dedicated interface device performs the format conversion and handles timing details. Given Data / Assumptions: Microprocessor or MCU provides data bytes in parallel. External channel expects asynchronous serial frames. Standard start/stop bit framing and optional parity are required. Concept / Approach: A UART (Universal Asynchronous Receiver/Transmitter) converts between parallel and serial data. On transmit, it frames bytes with start/stop (and parity) and shifts them out at the selected baud rate. On receive, it samples the serial line, reconstructs the byte, checks parity/stop, and presents parallel data to the system. Step-by-Step Solution: Load a byte in the UART transmit register in parallel.UART serializes the byte, appends start/stop/parity, and shifts it out.On receive, UART deserializes incoming bits into a byte.CPU reads the received byte in parallel and handles status flags (ready, overrun, framing error). Verification / Alternative check: MCU block diagrams and PC serial ports universally feature UARTs for parallel–serial translation, confirming their role as the standard interface component. Why Other Options Are Wrong: Key matrix: Scans switches; not a serial converter. Memory chip: Stores data; no serial framing. Serial-in, parallel-out: Does the opposite direction and lacks framing logic. ADC with SPI: SPI is synchronous serial; still not the generalized asynchronous serial interface described. Common Pitfalls: Mismatching baud rate, parity, or stop bits between endpoints. Ignoring buffering/interrupts, causing overruns at higher speeds. Final Answer: UART

Question 13

Register operations — In the context of flip-flop–based registers, what does “parallel-loading the register” mean?

Accepted Answer

Introduction: Registers can accept data either serially (one bit per clock) or in parallel (all bits at once). Understanding “parallel load” is essential when interfacing with data buses and when fast updates are required. Given Data / Assumptions: A multi-bit register built from flip-flops (example: 4-bit). Control input enables parallel loading on a specified clock edge. Data lines provide all bit values simultaneously. Concept / Approach: Parallel load means that, on the active clock edge with the load control asserted, the D inputs of all flip-flops are sampled simultaneously and transferred to Q outputs, updating the entire word in a single operation. This contrasts with shifting, which requires multiple clocks to move data through stages. Step-by-Step Solution: Present the desired word on the parallel data inputs (D3..D0).Assert the parallel load control (often active low).On the next clock edge, each flip-flop captures its corresponding bit.All Q outputs update together, completing the parallel load in one cycle. Verification / Alternative check: Datasheets for universal shift registers (e.g., 74HC194/195) define a dedicated load mode where all bits are latched concurrently, confirming the meaning of parallel loading. Why Other Options Are Wrong: Shifting simultaneously: Shifting is serial movement, not loading from external lines. Loading two flip-flops: Partial load is not “parallel-loading the register.” Disabling set/reset: A control safeguard, unrelated to data loading. Clear then shift: Describes a serial write sequence, not parallel load. Common Pitfalls: Confusing parallel load with asynchronous set/reset which forces all ones/zeros regardless of input data. Not meeting setup/hold times for all data inputs before the load edge. Final Answer: Loading data in all four flip-flops at the same time

Question 14

An asynchronous decade counter increases its value by ten for each clock pulse.

Accepted Answer

False

Question 15

A multiplexed display circuit uses a technique called time division modulation.

Accepted Answer

False

Question 16

The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

Accepted Answer

False

Question 17

Counters are common components in digital clocks.

Accepted Answer

True

Question 18

In an asynchronous counter, each state is clocked by the same pulse.

Accepted Answer

False

Question 19

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

Accepted Answer

False

Question 20

A serial-in, serial-out shift register transfers data from one line of a parallel bus to another line one bit at a time.

Accepted Answer

False

Sequential Logic Circuits Questions