Shift-register behavior — Which register type accepts a serial input bit-by-bit and outputs the stored data serially one bit at a time (i.e., serial in, serial out)?

Introduction:
Shift registers are used to convert between serial and parallel formats and to delay or manipulate bit streams. Identifying the correct register type is crucial for interfacing ICs and communication links.

Given Data / Assumptions:

• Input arrives one bit per clock.
• Output is also one bit per clock.
• No parallel load or read is required for the main function described.

Concept / Approach:

Register acronyms specify data flow: PIPO (parallel in, parallel out), SISO (serial in, serial out), SIPO (serial in, parallel out), PISO (parallel in, serial out). The described behavior matches SISO, often used as a simple delay line or pipeline of bits.

Step-by-Step Solution:

Verification / Alternative check:

Timing diagrams show a one-clock per stage latency from input to output, consistent with serial-in, serial-out operation used for digital delay lines.

Why Other Options Are Wrong:

• PIPO: No serial behavior; both input and output are parallel.
• SIPO: Serial input but parallel output.
• PISO: Parallel input but serial output.
• Bi-directional universal: Supports many modes; not uniquely SISO.

Common Pitfalls:

• Confusing SISO with SIPO/PISO during interface design.
• Ignoring required clocking and setup/hold constraints for reliable shifting.

Final Answer:

SISO