Asynchronous decade counter behavior: does an asynchronous (ripple) decade counter increase its count by ten for each incoming clock pulse, or does it advance by one and recycle after nine to form base-10 counting?

Introduction / Context:
Decade counters implement base-10 counting sequences used in timers, frequency dividers, and display drivers. Asynchronous (ripple) designs cascade flip-flops so that the clock ripples through stages. The question tests a common misunderstanding about the counting step size per clock edge.

Given Data / Assumptions:

• “Decade” means a modulo-10 sequence (0000 to 1001 in binary, then reset).
• Asynchronous implies the toggling of later stages is triggered by earlier stages, not by a common clock.
• Clock input is applied to the first stage only.

Concept / Approach:
A decade counter advances by one count per valid clock pulse. After reaching nine (1001), additional logic resets it to zero, creating a ten-state loop. There is no ten-step jump on each clock pulse. The modulo characteristic arises from the reset gating, not from an increment size of ten.

Step-by-Step Solution:

Verification / Alternative check:
Datasheets for 7490/4017 decade counters show truth tables with single-step advancement and a reset at the 10th state.

Why Other Options Are Wrong:
Increments by ten or two: not how decade counters operate.
Holds count until reset: contradicts counting function.

Common Pitfalls:
Confusing “divide-by-10” (frequency division by 10) with “add 10 to the count.” Divide-by-10 means one cycle per ten input pulses, not ten steps per pulse.

Final Answer:
Does not apply (increments by one each pulse)