Shift registers — SISO function clarified: A serial-in, serial-out (SISO) shift register is said to transfer data from one line of a parallel bus to another line one bit at a time. Is this description accurate, or is a SISO register primarily a serial time-delay element?

Introduction / Context:
Shift registers are categorized by how data enters and exits: SISO, SIPO, PISO, and PIPO. This question checks for a common misunderstanding—confusing the role of SISO registers with bus re-routing. A SISO register primarily shifts serial data through stages, acting like a delay line or serializer/deserializer component in longer chains.

Given Data / Assumptions:

• SISO: one serial input and one serial output.
• No parallel bus interface for input or output.
• Clocked shifting moves data one bit per cycle along cascaded flip-flops.

Concept / Approach:
A SISO shift register takes a single serial bit stream at its input and, on each clock, shifts the stored bits toward the serial output. It does not read from or write to multiple lines simultaneously (which would be “parallel”). Moving data “from one line of a parallel bus to another line” is not a SISO function; that would involve parallel access or bus routing, better addressed by multiplexers or PISO/SIPO variants when bridging between parallel and serial domains.

Step-by-Step Solution:

Verification / Alternative check:
Device datasheets (e.g., 74HC164) show serial input A/B and a single serial output Q_H, with no parallel load or read; timing diagrams confirm pure serial conduct without bus line selection.

Why Other Options Are Wrong:

• Correct: The statement is not correct for SISO devices.
• Valid only for tri-state buses: Tri-state buses are unrelated to SISO’s serial nature.
• True when 8-bit wide: Width does not create parallel access for SISO.
• Depends on endianness: Bit order conventions do not change the interface type.

Common Pitfalls:
Confusing SISO with PISO/SIPO; assuming “shift register” implies bus bridging; overlooking that SISO is best for bit-timing, delay, and serial pipelines.

Final Answer:
Incorrect