Step size of a 6-bit ADC over a 0–7 V input range An analog signal varies from 0 V to 7 V and is digitized by a 6-bit ADC. What analog value does each 1-LSB step represent on the digital output?

Introduction / Context:
Knowing the LSB size of an ADC allows quick estimation of quantization error and measurement resolution across a given input range.

Given Data / Assumptions:

• Input span: 0 to 7 V.
• Resolution: 6 bits → 64 codes.
• Ideal mid-tread behavior assumed for step size calculation.

Concept / Approach:
The LSB step size for an ideal ADC is Step = Full-Scale Range / 2^N. Here, N = 6, so 2^N = 64.

Step-by-Step Solution:

Verification / Alternative check:
2^6 = 64; 0.1 V × 64 = 6.4 V, so the precise 0.109375 V step is consistent with a 7 V span.

Why Other Options Are Wrong:

• 0.111 V: Close but not exact; it overestimates the step.
• 1.17 V / 0.857 V: These are far too large; they would imply minimal resolution (3–8 steps total).

Common Pitfalls:

• Dividing by 2^N − 1 for step size; while code count is 0..63, the step size calculation uses 2^N in ideal mid-tread models.

Final Answer:
0.109 V