Simultaneous (flash) A/D converters — identify the main drawback In a simultaneous, or flash, analog-to-digital converter, what is the primary disadvantage when targeting reasonable resolutions?

Introduction / Context:Flash ADCs achieve extreme speed by comparing the input against many reference thresholds in parallel. While this gives near-instant conversions, it incurs a steep hardware cost that grows exponentially with resolution.

Given Data / Assumptions:

• N-bit flash ADC uses 2^N − 1 comparators and a thermometer-to-binary encoder.
• Each additional bit doubles the number of comparators.

Concept / Approach:The key drawback is scaling: for N = 8 bits, 255 comparators are required; for 10 bits, 1023 comparators. This increases die area, power, input capacitance, and matching challenges, making higher resolutions impractical without time-interleaving or alternative architectures.

Step-by-Step Solution:Identify flash architecture's advantage: conversion speed.Identify the cost: comparator count = 2^N − 1.Associate impacts: power, heat, area, and calibration complexity.Hence, the main disadvantage is the large number of comparators required.

Verification / Alternative check:Industry practice uses flash for low resolution at very high speed or employs pipeline/SAR/sigma-delta for higher resolutions, precisely to avoid comparator explosion.

Why Other Options Are Wrong:

• Requiring the input voltage simultaneously: The input is common; this is not a drawback.
• Long conversion time: Flash is the fastest ADC type.
• Large number of output lines: Thermometer encoding is handled internally; external binary outputs scale reasonably.

Common Pitfalls:

• Assuming comparator count is linear with resolution—it's exponential.

Final Answer:the large number of comparators required to represent a reasonable sized binary number