Volatile main memory – which memory technology requires periodic refreshing to avoid data loss?

Introduction / Context:
Volatile memories lose data without power, but their internal storage mechanisms differ. Dynamic random-access memory (DRAM) stores bits as charge on tiny capacitors that leak over time. Recognizing which memory requires refresh is basic knowledge for system timing and controller design.

Given Data / Assumptions:

• Commodity main memory in PCs and many SoCs is DRAM.
• Refresh is performed by the memory controller automatically.
• Static RAM (SRAM) stores data in bistable latches, needing no refresh.

Concept / Approach:
DRAM cells are a capacitor plus access transistor. Leakage causes charge to decay, so rows must be periodically read and rewritten (refresh) within a retention window (for example, every 64 ms). SRAM cells, built from cross-coupled inverters, hold state as long as powered and do not need refresh. Nonvolatile memories (ROM/EPROM/EEPROM) retain data without power and also do not need refresh.

Step-by-Step Solution:

Verification / Alternative check:
DRAM datasheets specify refresh commands (AUTO REFRESH/SELF REFRESH) and retention times; SRAM datasheets have no such requirement.

Why Other Options Are Wrong:
SRAM is volatile but not refreshed; ROM/EPROM/EEPROM are nonvolatile and require no refresh either.

Common Pitfalls:
Assuming all volatile memories need refresh; only DRAM does because it stores charge rather than a stable latch state.

Final Answer:
DRAM