Address space expansion for RAM arrays: When increasing memory depth using a decoder and multiple RAM ICs, to which control/input pin of each memory should the decoder outputs be connected to select one device at a time?

Introduction / Context:
Expanding memory depth means using several identical memory ICs as banks so that more addressable locations exist at the same word width. A decoder examines high-order address bits and activates exactly one bank for any given address range. Correctly wiring the decoder outputs to the memory control pins is critical to avoid bus contention and ensure correct operation.

Given Data / Assumptions:

• Goal: expand address space (depth) using a decoder plus multiple RAM ICs.
• Each memory IC has Chip Enable (CE or /CS), Write Enable (WE or /WE), and Output Enable (OE or /OE).
• The system shares the same address and data buses across all banks.

Concept / Approach:
The decoder converts a subset of high-order address lines into one-hot control signals. The proper destination for these one-hot signals is the Chip Enable input of each memory IC. When a bank’s CE is asserted, it responds to the common address/data and WE/OE signals; all other banks remain disabled (outputs high-impedance), preventing bus contention.

Step-by-Step Solution:
1) Choose the number of banks N; a log2(N)-to-N decoder uses the top address bits to generate N select lines.2) Connect each decoder output to the CE of one memory IC.3) Tie all address lines (remaining bits) and the data bus in parallel across ICs.4) Fan out common control signals WE/OE to all ICs; only the enabled CE bank drives or stores data.

Verification / Alternative check:
Timing diagrams and bus truth tables show that with CE inactive, a device ignores reads/writes and tri-states outputs, proving CE is the correct selection pin for decoder outputs.

Why Other Options Are Wrong:
Most significant address inputs are data selectors, not bank selects. Data inputs carry payload, not selection. The read/write line defines operation type, not which chip is active.

Common Pitfalls:
Driving OE instead of CE (can still cause partial activation); leaving disabled chips with outputs enabled; forgetting to buffer signals when fan-out is large.

Final Answer:
The chip enable