Difficulty: Easy
Correct Answer: that must be refreshed periodically or it will lose storage
Explanation:
Introduction / Context:
Dynamic Random-Access Memory (DRAM) dominates main memory because it offers very high density at low cost per bit. Its defining characteristic is the need for periodic refresh due to charge leakage in its storage capacitors. Comparing DRAM with SRAM clarifies why refresh is necessary and how controllers manage it transparently to the CPU.
Given Data / Assumptions:
Concept / Approach:
Because stored charge decays, DRAM must be rewritten (refreshed) within a specified retention interval (e.g., every 64 ms or less depending on device). During refresh, rows are read and rewritten to restore charge. In contrast, SRAM uses cross-coupled inverters that hold state as long as power is present, without refresh, though it remains volatile.
Step-by-Step Solution:
1) Recognize DRAM cell structure and leakage.2) Use a refresh controller to cycle through all rows within the retention time.3) Memory remains coherent to the CPU because refresh is interleaved with normal accesses.4) Therefore, the accurate definition is that DRAM requires periodic refresh.
Verification / Alternative check:
Memory controller datasheets specify refresh rates (e.g., tREFI) and timing parameters (tRFC), confirming periodic refresh requirements.
Why Other Options Are Wrong:
Maintaining storage without power is nonvolatile behavior, not DRAM. “Data can never be altered” contradicts the writeable nature of RAM. “Maintains storage as long as power is applied” fits SRAM more closely but omits DRAM’s refresh need.
Common Pitfalls:
Thinking DRAM is nonvolatile; overlooking the performance impact of refresh on tight latency budgets.
Final Answer:
that must be refreshed periodically or it will lose storage
Discussion & Comments