Serial access devices – a memory that is accessed one location after another in sequence is best described as a ________.

Introduction / Context:
Not all storage devices provide random access. Serially accessed devices present data in a fixed order, which influences latency and interface design. Recognizing examples helps match devices to applications such as streaming and serializers/deserializers.

Given Data / Assumptions:

• Access proceeds in a fixed sequence rather than by arbitrary addressing.
• Output at any instant is the “next” stored value.
• Device may be implemented with flip-flops or dynamic techniques.

Concept / Approach:
A shift register stores bits in stages and shifts them left or right on clock edges, presenting or sampling one bit per step. This is the archetype of serial access storage. In contrast, RAM (read/write memory) is random access; ROM is random access (read-only); PLDs implement logic, not serial storage; associative caches access by content rather than sequence.

Step-by-Step Solution:

Verification / Alternative check:
Serial EEPROMs present bytes serially over SPI/I2C, but internally are random access memories; a pure shift register is the canonical serial access memory used for delay lines and serializers.

Why Other Options Are Wrong:
ROM and read/write RAM are random access; PLDs implement combinational/sequential logic, not serial storage; associative caches are content-addressable, not serial.

Common Pitfalls:
Confusing serial interface with serial access; some RAMs use serial interfaces but allow random addressing internally.

Final Answer:
shift register