Behavior of the J–K flip-flop at J = 1 and K = 1: Does the J–K flip-flop remove the SR “invalid” condition by toggling the stored state on the active clock transition when both inputs are HIGH?

Digital Electronics Flip-Flops Difficulty: Easy
Choose an option
  • A
    Correct
  • B
    Incorrect
  • C
    Only true for positive-edge devices
  • D
    Only when asynchronous clear is asserted

Answer

Correct Answer: Correct

Explanation

Introduction / Context: The SR flip-flop suffers from an invalid state when S = 1 and R = 1 simultaneously. The J–K flip-flop was developed to overcome this limitation while retaining set, reset, and hold behaviors. One hallmark of the J–K device is its “toggle” action when both inputs are asserted together at the clock edge.

Given Data / Assumptions:

  • A clocked J–K flip-flop is considered (edge-triggered or master–slave equivalent).
  • Inputs J and K are both HIGH (logic 1) during the valid setup/hold window around the active clock edge.
  • No asynchronous preset/clear is active.

Concept / Approach: The truth behavior of a J–K flip-flop includes: J = 0, K = 0 → hold; J = 1, K = 0 → set; J = 0, K = 1 → reset; J = 1, K = 1 → toggle (Q(next) = Q’(current)). This elegantly resolves the SR invalid combination by defining a deterministic response—state inversion—on the clock transition.

Step-by-Step Solution:

Assume Q(current) = 0; with J = 1 and K = 1 at the edge → Q(next) = 1.Assume Q(current) = 1; with J = 1 and K = 1 at the edge → Q(next) = 0.Thus, each qualifying clock edge flips the stored bit, realizing a divide-by-two stage when driven continuously.This behavior is independent of edge polarity (positive or negative), provided timing requirements are met.

Verification / Alternative check:

Configure J = K = 1 and clock at frequency f; the Q output toggles at f/2, confirming the toggle rule.

Why Other Options Are Wrong:

Incorrect: Denies a defining property of the J–K flip-flop.Only true for positive-edge devices: Toggle applies to either edge polarity devices; the edge type only sets the sampling instant.Only when asynchronous clear is asserted: Asynchronous clear forces reset, not toggle.

Common Pitfalls:

Violating setup/hold for J and K, which can prevent reliable toggling.Assuming toggle during level intervals; toggle occurs at the active edge only.

Final Answer:

Correct
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