NOR-gate S–R latch reasoning: For a NOR-based S–R flip-flop (latch), if the outputs are Q = 1 and Q̄ = 0 (the set state), what are the input levels S and R?

Introduction / Context:
The classic S–R latch built from cross-coupled NOR gates has two control inputs: Set (S) and Reset (R). Understanding the correspondence between input assertions and output states is essential for correct design and debugging.

Given Data / Assumptions:

• NOR-based S–R latch (active-high S and R).
• Outputs: Q and Q̄ are complements in valid states.
• We are given Q = 1 and Q̄ = 0, i.e., the set state.

Concept / Approach:
For NOR-gate implementation, an asserted input is logic 1. Driving S = 1 forces Q = 1 regardless of feedback, provided R = 0. Conversely, R = 1 forces Q = 0. With both low (S = 0, R = 0), the latch holds its previous state. S = R = 1 is invalid for a NOR latch.

Step-by-Step Solution:

Verification / Alternative check:
Truth summary: S,R = 1,0 → set; 0,1 → reset; 0,0 → hold; 1,1 → invalid. The given outputs correspond to the set line asserted.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing NOR- and NAND-based latch conventions; forgetting that S = R = 1 (NOR) is invalid; assuming hold rather than considering the need to assert S to set.

Final Answer:
S = 1, R = 0