Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:Flip-flops may accept two categories of control: synchronous (sampled by the clock) and asynchronous (override the state regardless of the clock). Recognizing the difference is central to safe design and timing closure.
Given Data / Assumptions:
Concept / Approach:Asynchronous control immediately forces the state; therefore, it must be deasserted synchronously (or safely) to avoid recovery/removal violations. Synchronous controls (like D, J/K) affect the state only on the active clock edge.
Step-by-Step Solution:
Identify inputs that bypass the clock (preset/clear).Note they act immediately (subject to propagation delay), not at the edge.Hence, by definition, these are asynchronous inputs.Therefore, the statement is correct.Verification / Alternative check:Datasheets label these pins as asynchronous and specify recovery/removal times rather than setup/hold.
Why Other Options Are Wrong:
Incorrect: Contradicts how preset/clear operate.Only true for latches or only for positive-edge: Asynchronicity is independent of clocking style or edge polarity.Common Pitfalls:Asserting asynchronous signals near a clock edge without meeting recovery/removal; leaving async pins floating; assuming they are sampled by the clock.
Final Answer:Correct
Discussion & Comments