Synchronous vs. asynchronous logic — classification check: Simple gate networks (pure combinational logic) have no clocked storage and thus are asynchronous; transparent S–R latches are level-sensitive, not edge-synchronous. Evaluate the statement: “Simple gate circuits, combinational logic, and transparent S–R flip-flops are synchronous.”

Introduction / Context:
In digital design, “synchronous” implies that state changes happen in lockstep with a timing reference (usually a clock edge). Combinational circuits lack memory and do not synchronize to a clock, and transparent latches follow inputs while enabled rather than at discrete edges.

Given Data / Assumptions:

• Simple gate circuits: no storage, purely input-driven.
• Combinational logic: outputs are functions of current inputs only.
• Transparent S–R latch: level-sensitive; follows inputs during enable.

Concept / Approach:
Because combinational logic has no concept of “state update on a clock,” it is asynchronous. Transparent latches change state whenever the enable is active (level), not strictly at a clock edge. Hence calling all of these “synchronous” is incorrect in the conventional clocked-systems sense.

Step-by-Step Solution:

Verification / Alternative check:
Timing analysis: combinational propagation delays exist without reference to a clock; latches require careful enable timing to avoid transparency hazards, reinforcing they are not purely edge-synchronous.

Why Other Options Are Wrong:

• Correct: Contradicted by definitions.
• “Only synchronous when gated by RC” or “fan-in limited to 2” or “Schmitt-trigger gates”: These conditions do not change the fundamental classification.

Common Pitfalls:
Equating “has timing” with “is synchronous”; ignoring the difference between level gating and edge triggering; overlooking that combinational logic has no internal state to synchronize.

Final Answer:
Incorrect