Introduction:
Dynamic random-access memory (DRAM) stores data as charge on tiny capacitors. Because these capacitors leak, DRAM requires periodic refresh to maintain data integrity. The statement claims the opposite, so we must evaluate and correct it, reinforcing key memory-technology differences between DRAM and SRAM.
Given Data / Assumptions:
- DRAM cells use 1T1C (one transistor, one capacitor) structures.
- Leakage currents cause charge decay over milliseconds.
- Memory controllers perform refresh operations at required intervals (e.g., all rows within tREFI constraints).
Concept / Approach:
DRAM's density advantage comes at the cost of mandatory refresh. Each row must be periodically accessed to restore charge (read and rewrite). Therefore a claimed advantage of "no refresh needed" is incorrect. "No refresh" is an attribute of SRAM, which maintains state statically while power is applied.
Step-by-Step Solution:
Understand storage: DRAM bit = charge on a capacitor; charge leaks over time.Controller action: refresh cycles access each row to restore lost charge.Conclusion: refresh is required; lack of refresh is not a DRAM advantage.
Verification / Alternative check:
JEDEC standards specify refresh intervals (e.g., 64 ms typical at room temperature) and timing parameters like tRFC, tREFI, proving refresh is intrinsic.
Why Other Options Are Wrong:
Correct: Would invert the defining behavior of DRAM.True only below 1 Hz clock: Refresh is independent of CPU clock; it is a memory requirement.Depends solely on bus width: Bus width does not remove the need for refresh.
Common Pitfalls:
Confusing DRAM with SRAM.Assuming self-refresh during low power eliminates refresh entirely; it merely automates it.
Final Answer:
Incorrect
Discussion & Comments