DRAM pin-count reduction technique: To reduce the number of pins on high-capacity DRAM chips, what address technique is used so a single set of pins can carry both row and column addresses at different times?

Introduction / Context:
Dynamic RAM devices require many address lines, but package pin counts must be constrained for cost and size. The industry solution is to time-multiplex the address bus, sending row and column addresses sequentially over the same pins.

Given Data / Assumptions:

• High-capacity DRAM with large address space.
• Desire to limit package pin count.
• Standard DRAM control pins: RAS (row address strobe) and CAS (column address strobe).

Concept / Approach:
Address multiplexing uses the same physical address pins twice per access: first the controller presents the row address and asserts RAS; then it presents the column address and asserts CAS. Internally, DRAM latches each portion separately, allowing many address bits with fewer external pins.

Step-by-Step Solution:

Verification / Alternative check:
Pinouts and timing diagrams for common DRAMs show A0..An used with RAS/CAS to latch row and column portions of the address.

Why Other Options Are Wrong:

• conversion/programming/firmware: These terms do not describe hardware pin reuse for addressing.

Common Pitfalls:
Confusing multiplexing with bank interleaving or burst modes; overlooking the role of RAS/CAS strobes in timing.

Final Answer:
multiplexing