Legacy DRAM pinout fact check: For the TMS44100 DRAM device, how many address inputs (shared via row/column multiplexing) are provided on the package?

Introduction / Context:
Historical DRAM parts commonly multiplexed row and column addresses to limit package pins. Recognizing typical address-pin counts helps in decoding maps and designing compatible memory controllers for legacy systems or educational labs.

Given Data / Assumptions:

• Device: TMS44100 (legacy DRAM).
• Standard DRAM practice: present row and column addresses over the same address pins.
• Question asks for the number of external address inputs (pins), not total logical address bits stored internally.

Concept / Approach:
Many classic high-density DRAMs expose 10 external address pins that are time-multiplexed by RAS and CAS strobes (10 for row and the same 10 for column internally). This supports large address spaces without requiring 20 physical address pins. Thus, the package typically lists A0–A9 for addresses, for a total of 10 external address inputs.

Step-by-Step Solution:

Verification / Alternative check:
Typical datasheets for 1 Mbit-era DRAMs show 10 address inputs, consistent with multiplexing and common package pin budgets of that generation.

Why Other Options Are Wrong:

• 11/12/13: Do not match the standard pinout practice for this device class; more pins would counter the purpose of address multiplexing.

Common Pitfalls:
Confusing internal logical address width with the count of external address pins; overlooking multiplexing’s impact on pin budgeting.

Final Answer:
10