Integrated-Circuit Logic Families Questions

• The major advantage of CMOS logic circuits over TTL is very low power consumption.
• The abbreviated designator for a HIGH input voltage is VIH.
• CMOS stands for "complementary metal-oxide semiconductors" and the FETs are normally enhancement mode devices.
• The TTL HIGH level source current is higher than the LOW level sinking current.
• Usually P-MOS and N-MOS circuits are identical with the exception of the voltage polarities.
• The time it takes for a square wave to go from 10% to 90% of its voltage level is called propagation delay.
• A common means for measuring and comparing the overall performance of an IC family is the speed-power product.
• The noise margin for TTL is 0.8 V.
• The data sheet for the 74 series of TTL ICs shows that Vcc has a range of 4.5 V to 5.5 V.
• The dc noise margins calculated using the proper values from a standard TTL data sheet are the worst-case margins. The typical dc noise margins are usually somewhat higher.
• The logic family with the highest maximum clock frequency is HS-TTL.
• ECL gates are noted for their high frequency capability and small output voltage swing.
• The upper transistor of a totem-pole output is OFF when the gate output is low.
• The major advantage of TTL logic circuits over CMOS is lower propagation delay.
• The principal advantage of MOS ICs over TTL ICs is their fast operating speed.
• Due to the extremely low power requirements of CMOS logic circuits, any number of CMOS and TTL gates can be interconnected.
• Most TTL gates use the totem-pole output arrangement.
• The output current capability for a HIGH output condition is called a source current.
• The maximum output voltage recognized as a LOW by a TTL gate is 2.0 V.
• When the outputs of several standard TTL gates are connected together, the gate outputs produce more fan-out.