Introduction / Context:
CMOS ICs are prized for their extremely low static (DC) power, but when they switch, they consume dynamic power to charge and discharge node capacitances. This question tests whether you recognize the qualitative dependence of CMOS power on operating frequency and on the physical size/capacitance of gates.
Given Data / Assumptions:
- Total CMOS power is the sum of dynamic (switching) power and leakage (static) power.
- Dynamic power is often modeled as Pdyn = α * Cload * V^2 * f, where α is the activity factor, Cload the switched capacitance.
- Gate size and interconnect scale affect the effective capacitance Cload.
- Supply voltage V is treated as constant for this qualitative question.
Concept / Approach:
With Pdyn proportional to both the switched capacitance and the operating frequency, any increase in frequency or node capacitance leads directly to higher power. Larger transistors and larger fan-out typically imply larger capacitances, while slowing the clock (lower f) lowers dynamic power. Leakage can matter at very small geometries, but the core relationship above remains fundamental.
Step-by-Step Solution:
Express dynamic power: Pdyn = α * Cload * V^2 * f.Hold α, V roughly constant; examine dependence on f → Pdyn increases as f increases.Examine dependence on Cload → Cload grows with gate size and fan-out, increasing Pdyn.Therefore, statements that power increases with frequency (and with gate size) are qualitatively correct.
Verification / Alternative check:
Power measurements on CMOS systems scale near-linearly with clock frequency when voltage and workload are fixed.
Why Other Options Are Wrong:
decrease with frequency: Contradicts Pdyn ∝ f.decrease with gate size: Larger devices mean higher capacitance; power does not decrease.increase with gate size: This is also qualitatively true, but the prompt asks which effect regarding frequency is correct; among the provided single best answers, “increase with frequency” is the direct frequency relationship.
Common Pitfalls:
Confusing static leakage with dynamic power; in classic CMOS, dynamic dominates at moderate technology nodes.Ignoring activity factor α; even with low α, the f and Cload relationships hold.
Final Answer:
increase with frequency
Discussion & Comments