Transparent D latch — enable-controlled behavior For a level-sensitive D latch, which statement correctly describes the relationship between input D and output Q as a function of the enable input EN?

Introduction / Context:
A D latch is a level-sensitive storage element. When enabled, it is transparent and passes input changes to the output; when disabled, it holds the last captured value. Recognizing this behavior is critical when building registers, pipelines, and two-phase latch-based timing systems.

Given Data / Assumptions:

• Device: D (data) latch with enable input EN.
• Polarity: EN is active-HIGH in the typical configuration.
• Outputs: Q (and often Q' as complement).

Concept / Approach:
Transparency means that whenever EN is asserted HIGH, the internal gating path opens and Q immediately follows D (limited by propagation delay). When EN goes LOW, the path closes and the latch stores the last D value at that moment, maintaining Q until EN is asserted again.

Step-by-Step Solution:

Verification / Alternative check:
Examine timing diagrams: with EN HIGH, toggling D produces corresponding toggles on Q after a small delay; with EN LOW, Q remains flat regardless of D activity.

Why Other Options Are Wrong:

• Following at EN LOW or always HIGH output contradict latch operation.
• Opposite at EN LOW implies inversion behavior that is not part of a standard D latch.

Common Pitfalls:
Confusing a D latch with an edge-triggered D flip-flop (which samples only at an edge), or misinterpreting EN polarity in specific vendor symbols.

Final Answer:
the Q output follows the D input when EN is HIGH