Classic S–R flip-flop — key limitation What is one commonly cited disadvantage of the basic S–R (Set–Reset) flip-flop implementation?

Introduction / Context:
The S–R flip-flop is the simplest bistable built from cross-coupled gates (NOR or NAND). While educationally valuable, it has a notable limitation that makes it less desirable as a universal storage element in synchronous designs. Recognizing this limitation helps you choose D, J–K, or T flip-flops where deterministic behavior is required.

Given Data / Assumptions:

• Standard S–R behavior using either NOR (active-HIGH S,R) or NAND (active-LOW S,R) implementations.
• Two outputs: Q and Q' (complement).
• No explicit clock in the simplest configuration; synchronous versions exist but inherit the same limitation.

Concept / Approach:
For the NOR-based S–R latch, the input combination S = 1 and R = 1 is forbidden because both outputs attempt to be driven LOW simultaneously, violating the intended complementary relationship. For the NAND version (active-LOW inputs), the forbidden combination is S = 0 and R = 0. This undefined/invalid state leads to unpredictable results when the inputs return to the non-asserted condition, including possible metastability or output ambiguity.

Step-by-Step Solution:

Verification / Alternative check:
Simulate the latch: drive the forbidden inputs, then release them; observe output dependency on gate delays (race), illustrating the unpredictability.

Why Other Options Are Wrong:

• No enable input: not a fundamental disadvantage; enables can be added externally.
• No clock input: true for the simple latch, but clocked S–R flip-flops exist.
• Single output: incorrect; S–R latches provide Q and Q'.

Common Pitfalls:
Assuming the invalid state is harmless, or forgetting which input polarity (NOR vs. NAND) defines the forbidden combination.

Final Answer:
It has an invalid state.