Curioustab

Home » Digital Electronics » Flip-Flops

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

parity error checking
ones catching
digital discrimination
digital filtering

Correct Answer: ones catching

← Previous Question Next Question→

More Questions from Flip-Flops

What is one disadvantage of an S-R flip-flop?
Which of the following describes the operation of a positive edge-triggered D flip-flop?
Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
The symbols on this flip-flop device indicate ________.
To completely load and then unload an 8-bit register requires how many clock pulses?
A 555 operating as a monostable multivibrator has a C1 = 100 µF. Determine R1 for a pulse width of 500 ms.
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
Propagation delay time, tPLH, is measured from the ________.
The output pulse width of a 555 monostable circuit with R1 = 4.7 kΩ and C1 = 47 µF is ________.

Discussion & Comments

No comments yet. Be the first to comment!

Join Discussion