J–K flip-flop hazard — naming the issue while clock is HIGH The phenomenon where unwanted signals on J and K are interpreted (causing spurious toggles) while the clock input Cp is HIGH is called what?

Introduction / Context:
Level-sensitive J–K flip-flops can exhibit problematic behavior if their inputs change while the clock is at the active level. Understanding the specific terminology for these hazards helps in recognizing, explaining, and fixing erratic toggling in counters or control logic during lab diagnostics.

Given Data / Assumptions:

• Device: J–K flip-flop with level-sensitive gating when Cp is HIGH.
• Inputs J and K might experience glitches or asynchronous changes.
• We focus on the undesired toggling that occurs during the active clock level.

Concept / Approach:
When Cp is HIGH and the internal gating is transparent, a stray 1 present on J or K may be captured, producing an unintended state change. This specific behavior is colloquially termed ones catching, reflecting that a momentary logic-1 on an input is caught and affects the output when it should not.

Step-by-Step Solution:

Verification / Alternative check:
Scope measurements often show brief spikes on J/K coincident with Cp HIGH leading to unexpected Q transitions; adding input synchronizers or converting to edge-triggered devices mitigates this.

Why Other Options Are Wrong:

• Parity error checking: unrelated to flip-flop internal timing; pertains to data integrity methods.
• Digital discrimination/digital filtering: generic signal-processing terms, not the classic flip-flop hazard name.

Common Pitfalls:
Failing to synchronize asynchronous inputs, letting combinational hazards feed J/K directly, or using excessive clock HIGH width with level-sensitive designs.

Final Answer:
ones catching