Flip-Flops problems
- 1. On a J-K flip-flop, when is the flip-flop in a hold condition?
Options- A. J = 0, K = 0
- B. J = 1, K = 0
- C. J = 0, K = 1
- D. J = 1, K = 1 Discuss
Correct Answer: J = 0, K = 0
- 2. A positive edge-triggered D flip-flop will store a 1 when ________.
Options- A. the D input is HIGH and the clock transitions from HIGH to LOW
- B. the D input is HIGH and the clock transitions from LOW to HIGH
- C. the D input is HIGH and the clock is LOW
- D. the D input is HIGH and the clock is HIGH Discuss
Correct Answer: the D input is HIGH and the clock transitions from LOW to HIGH
- 3. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
Options- A. constantly LOW
- B. constantly HIGH
- C. a 20 kHz square wave
- D. a 10 kHz square wave Discuss
Correct Answer: a 10 kHz square wave
- 4. When is a flip-flop said to be transparent?
Options- A. when the Q output is opposite the input
- B. when the Q output follows the input
- C. when you can see through the IC packaging Discuss
Correct Answer: when the Q output follows the input
- 5. In VHDL, in which declaration section is a COMPONENT declared?
Options- A. Architecture
- B. Library
- C. Entity
- D. Port map Discuss
Correct Answer: Architecture
- 6. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
Options- A. True
- B. False Discuss
Correct Answer: False
- 7. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
Options- A. edge-detection circuit.
- B. NOR latch.
- C. NAND latch.
- D. pulse-steering circuit. Discuss
Correct Answer: edge-detection circuit.
- 8. In VHDL, how many inputs will a primitive JK flip-flop have?
Options- A. 2
- B. 3
- C. 4
- D. 5 Discuss
Correct Answer: 5
- 9. One example of the use of an S-R flip-flop is as a(n):
Options- A. racer
- B. astable oscillator
- C. binary storage register
- D. transition pulse generator Discuss
Correct Answer: binary storage register
- 10. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
Options- A. 10.24 kHz
- B. 5 kHz
- C. 30.24 kHz
- D. 15 kHz Discuss
Correct Answer: 5 kHz
More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.