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Flip-Flops problems

  • 1. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

  • Options
  • A. S = 1, R = 1
  • B. S = 1, R = 0
  • C. S = 0, R = 1
  • D. S = 0, R = 0
    • Discuss
  • 2. The advantage of a J-K flip-flop over an S-R FF is that ________.

  • Options
  • A. it has fewer gates
  • B. it has only one output
  • C. it has no invalid states
  • D. it does not require a clock input
    • Discuss
  • 3. A major drawback to an Digital Electronics Flip-Flops: A major drawback to an latch is its ________.

  • Options
  • A. complexity
  • B. slow speed
  • C. invalid condition
  • D. latch mode
    • Discuss
  • 4. The action of ________ a FF or latch is also called resetting.

  • Options
  • A. breaking
  • B. clearing
  • C. freeing
  • D. changing
    • Discuss
  • 5. The ________ is the time interval immediately following the active transition of the clock signal.

  • Options
  • A. hold time
  • B. setup time
  • C. over-time
  • D. hang-time
    • Discuss
  • 6. The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

  • Options
  • A. logic level
  • B. flip-flop
  • C. edge-detector circuit
  • D. toggle detector
    • Discuss
  • 7. Assume an Digital Electronics Flip-Flops: Assume an latch, made latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

  • Options
  • A.
  • B.
  • C.
  • D.
    • Discuss
  • 8. The term hold always means ________.

  • Options
  • A.
  • B.
  • C.
  • D. no change
    • Discuss
  • 9. The asynchronous inputs on a J-K flip-flop ________.

  • Options
  • A. are normally not at the active level at the same time
  • B. take precedence over the J and K inputs
  • C. do not require a clock pulse to affect the output
  • D. all of the above
    • Discuss
  • 10. A flip-flop operation is described as a toggle when the result after a clock is ________.

  • Options
  • A.
  • B.
  • C.
  • D. change to opposite states
    • Discuss

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