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Flip-Flops problems


  • 1. A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

  • Options
  • A. True
  • B. False
  • Discuss
  • 2. All multivibrators require feedback.

  • Options
  • A. True
  • B. False
  • Discuss
  • 3. Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.

  • Options
  • A. True
  • B. False
  • Discuss
  • 4. The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.

  • Options
  • A. True
  • B. False
  • Discuss
  • 5. VHDL does require a special designation for an output with a feedback.

  • Options
  • A. True
  • B. False
  • Discuss
  • 6. Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

  • Options
  • A. True
  • B. False
  • Discuss
  • 7. Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.

  • Options
  • A. True
  • B. False
  • Discuss
  • 8. The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

  • Options
  • A. True
  • B. False
  • Discuss
  • 9. A TOGGLE input to a J-K flip-flop causes the Q and Digital Electronics Flip-Flops: A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.

  • Options
  • A. True
  • B. False
  • Discuss
  • 10. Pulse-triggered or level-triggered devices are the same.

  • Options
  • A. True
  • B. False
  • Discuss

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