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Flip-Flops problems

  • 1. The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

  • Options
  • A. PRE, CLR, LOW
  • B. ON, OFF, HIGH
  • C. START, STOP, LOW
  • D. SET, RESET, HIGH
    • Discuss
  • 2. What type of multivibrator is a latch?

  • Options
  • A. Astable
  • B. Monostable
  • C. Bistable
  • D. It depends on the type of latch.
    • Discuss
  • 3. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

  • Options
  • A. 3
  • B. 7
  • C. 10
  • D. 13
    • Discuss
  • 4. The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.

    Digital Electronics Flip-Flops: The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are _____

  • Options
  • A. point 4
  • B. points 3 and 4
  • C. points 1 and 2
  • D. points 4 and 5
    • Discuss
  • 5. A gated S-R flip-flop goes into the CLEAR condition when ________.

  • Options
  • A. S is HIGH; R is LOW; EN is HIGH
  • B. S is LOW; R is HIGH; EN is HIGH
  • C. S is LOW; R is HIGH; EN is LOW
  • D. S is HIGH; R is LOW; EN is LOW
    • Discuss
  • 6. The signal used to identify edge-triggered flip-flops is ________.

  • Options
  • A. a bubble on the clock input
  • B. an inverted "L" on the output
  • C. the letter "E" on the enable input
  • D. a triangle on the clock input
    • Discuss
  • 7. A gated D latch does not have ________.

  • Options
  • A. a clock input
  • B. an enable input
  • C. a output
  • D. steering gates
    • Discuss
  • 8. A positive edge-triggered flip-flop will accept inputs only when the clock ________.

  • Options
  • A. is LOW
  • B. changes from HIGH to LOW
  • C. is HIGH
  • D. changes from LOW to HIGH
    • Discuss
  • 9. A gated S-R flip-flop is in the hold condition whenever ________.

  • Options
  • A. the Gate Enable is HIGH
  • B. the Gate Enable is LOW
  • C. the S and R inputs are both LOW
  • D. the Gate Enable is HIGH and the S and R inputs are both LOW
    • Discuss
  • 10. The postponed symbol (Digital Electronics Flip-Flops: The postponed symbol ()) on the output of a flip-flop identifies it as being ________.

  • Options
  • A. a D flip-flop
  • B. a J-K flip-flop
  • C. pulse triggered
  • D. trailing edge-triggered
    • Discuss

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