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Flip-Flops problems
1. A 555 operating as a monostable multivibrator has an R
1
of 1 MΩ. Determine C
1
for a pulse width of 2 s.
Options
A. 1.8 µF
B. 18 F
C. 18 pF
D. 18 nF
Show Answer
Scratch Pad
Discuss
Correct Answer: 1.8 µF
2. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
Options
A. 00
B. 11
C. 01
D. 10
Show Answer
Scratch Pad
Discuss
Correct Answer: 00
3. If both inputs of an
S-R
flip-flop are LOW, what will happen when the clock goes high?
Options
A. No change will occur in the output.
B. An invalid state will exist.
C. The output will toggle.
D. The output will reset.
Show Answer
Scratch Pad
Discuss
Correct Answer: No change will occur in the output.
4. Which of the following is not generally associated with flip-flops?
Options
A. Hold time
B. Propagation delay time
C. Interval time
D. Set up time
Show Answer
Scratch Pad
Discuss
Correct Answer: Interval time
5. Edge-triggered flip-flops must have:
Options
A. very fast response times
B. at least two inputs to handle rising and falling edges
C. positive edge-detection circuits
D. negative edge-detection circuits
Show Answer
Scratch Pad
Discuss
Correct Answer: positive edge-detection circuits
6. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options
A.
CLK
= NGT,
D
= 0
B.
CLK
= PGT,
D
= 0
C. CLOCK NGT,
D
= 1
D. CLOCK PGT,
D
= 1
E.
CLK
= NGT,
D
= 0, CLOCK NGT,
D
= 1
Show Answer
Scratch Pad
Discuss
Correct Answer: CLOCK PGT,
D
= 1
7. An active-HIGH input S-R latch has a 1 on the
S
input and a 0 on the
R
input. What state is the latch in?
Options
A.
B.
C.
D.
Show Answer
Scratch Pad
Discuss
Correct Answer:
8. The pulse width of a one-shot circuit is determined by ________.
Options
A. a resistor and capacitor
B. two resistors
C. two capacitors
D. none of the above
Show Answer
Scratch Pad
Discuss
Correct Answer: a resistor and capacitor
9. Which of the following is correct for a D latch?
Options
A. The output toggles if one of the inputs is held HIGH.
B.
Q
output follows the input
D
when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D. The output complement follows the input when enabled.
Show Answer
Scratch Pad
Discuss
Correct Answer:
Q
output follows the input
D
when the enable is HIGH.
10. Gated
S-R
flip-flops are called asynchronous because the output responds immediately to input changes.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
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More in Digital Electronics:
Boolean Algebra and Logic Simplification
Code Converters and Multiplexers
Combinational Logic Analysis
Combinational Logic Circuits
Computers
Counters
Describing Logic Circuits
Digital Arithmetic Operations and Circuits
Digital Concepts
Digital Design
Digital Signal Processing
Digital System Projects Using HDL
Ex-OR and Ex-NOR Gates
Flip-Flops
Integrated-Circuit Logic Families
Integrated Circuit Technologies
Interfacing to the Analog World
Logic Families and Their Characteristics
Logic Gates
Memory and Storage
Microprocessor Fundamentals
MSI Logic Circuits
Multivibrators and 555 Timer
Number Systems and Codes
Programmable Logic Device
Shift Registers
Signals and Switches
The 8051 Microcontroller