Question 1

Three-input NOR gate condition for HIGH output From the truth table of a 3-input NOR gate, which input combination (A, B, C) produces a HIGH (logic 1) output X?

Accepted Answer

Introduction / Context: NOR gates are universal elements. Understanding their truth behavior is essential for designing active-LOW control signals and wired-OR types of logic in digital systems. Given Data / Assumptions: 3-input NOR with inputs A, B, C, output X. NOR is NOT(OR) across all inputs. Logic levels are ideal (no analog thresholds considered). Concept / Approach: The NOR function is X = NOT(A + B + C). The OR of any input being HIGH yields 1, and after inversion, the output becomes 0. Therefore, the only way for X to be 1 is for the OR term to be 0, which requires A = B = C = 0. Step-by-Step Solution: Compute OR: S = A + B + C.If any of A, B, or C equals 1, then S = 1.NOR output: X = NOT(S). Thus, if S = 1 → X = 0; if S = 0 → X = 1.S = 0 only when A = 0, B = 0, and C = 0. Verification / Alternative check: Truth table enumeration shows that the line with A = 0, B = 0, C = 0 is the only row producing X = 1; all other rows produce X = 0. Why Other Options Are Wrong: Any case with at least one 1 (like 100, 010, 001, 110, 101, 011, 111) makes the OR term 1 and the NOR output 0. Common Pitfalls: Thinking NOR is the same as NAND; they complement different base operations. Forgetting that the presence of even a single HIGH at the input of OR forces the OR result to HIGH. Final Answer: A = 0, B = 0, C = 0

Question 2

Exclusive-OR (XOR) behavior For a standard 2-input exclusive-OR gate, under which condition does the output go HIGH (logic 1)?

Accepted Answer

Introduction / Context: The exclusive-OR (XOR) gate is central to parity generation, adders, and data comparison circuits. Knowing its defining condition helps when analyzing arithmetic logic units and error-checking networks. Given Data / Assumptions: 2-input XOR with inputs A and B; output X. Logic levels are ideal 0 or 1. Definition: XOR outputs 1 if exactly one input is 1. Concept / Approach: The canonical expression for XOR is X = A * NOT B + NOT A * B. This evaluates to 1 when the inputs differ (one HIGH, one LOW). When both are the same (both 0 or both 1), each product term becomes 0, yielding X = 0. Step-by-Step Solution: Case A=0, B=0 → X = 0 * 1 + 1 * 0 = 0.Case A=0, B=1 → X = 0 * 0 + 1 * 1 = 1.Case A=1, B=0 → X = 1 * 1 + 0 * 0 = 1.Case A=1, B=1 → X = 1 * 0 + 0 * 1 = 0. Verification / Alternative check: XOR may be viewed as “inequality detector.” If A ≠ B, output is 1; if A = B, output is 0. This matches the gate’s symbol and widespread usage in comparators. Why Other Options Are Wrong: “all inputs are LOW” gives output 0 with XOR. “all inputs are HIGH” also gives output 0. “none of the above” is invalid because “inputs are unequal” is the correct defining property. Common Pitfalls: Confusing XOR with OR. OR is HIGH when any input is HIGH, including both HIGH; XOR is LOW when both are HIGH. Assuming XOR is just “either input” without excluding “both.” Final Answer: the inputs are unequal

Question 3

Exclusive-NOR (XNOR) behavior For a standard 2-input exclusive-NOR gate, under which condition does the output go HIGH (logic 1)?

Accepted Answer

Introduction / Context: Exclusive-NOR (XNOR) is the logical complement of XOR and is often used as an equality detector in digital comparators, address match circuits, and error-checking logic. Given Data / Assumptions: 2-input XNOR with inputs A, B and output X. XNOR = NOT(XOR). Ideal logic levels 0 and 1. Concept / Approach: Since XOR outputs 1 when inputs differ, XNOR outputs 1 when inputs are the same. Common expression: X = A * B + NOT A * NOT B. This evaluates to 1 for (0,0) and (1,1) input pairs only. Step-by-Step Solution: Case A=0, B=0 → X = 0 * 0 + 1 * 1 = 1.Case A=0, B=1 → X = 0 * 1 + 1 * 0 = 0.Case A=1, B=0 → X = 1 * 0 + 0 * 1 = 0.Case A=1, B=1 → X = 1 * 1 + 0 * 0 = 1. Verification / Alternative check: Think of XNOR as “logical equality.” If A equals B, the output is HIGH; otherwise, LOW. Many digital comparators chain XNORs across bit-pairs and OR the inverted results to detect mismatches. Why Other Options Are Wrong: “one HIGH, one LOW” describes XOR, not XNOR. “inputs are unequal” is XOR’s condition for HIGH, the opposite of XNOR. “none of the above” is false because “inputs are equal” is correct. Common Pitfalls: Assuming XNOR is the same as OR or AND; it is a distinct equality operator. Forgetting that XNOR is the inverse of XOR and thus complements its truth table. Final Answer: the inputs are equal

Question 4

Logic family comparison — TTL vs. CMOS Identify one classic advantage that transistor–transistor logic (TTL) historically has over CMOS logic families.

Accepted Answer

Introduction / Context: Different logic families (TTL, CMOS, ECL, etc.) offer trade-offs in speed, power, noise immunity, and robustness. Knowing their comparative advantages guides part selection for legacy designs and understanding historical choices in digital systems. Given Data / Assumptions: TTL refers to bipolar transistor logic (e.g., 74xx). CMOS refers to complementary MOS logic (e.g., 74HC/74HCT/4000-series). We refer to classic baseline characteristics, not special high-speed subfamilies. Concept / Approach: Historically, standard TTL offered higher switching speed than early CMOS at comparable supply voltages, though consuming more power. Modern CMOS families have largely closed or exceeded this gap, but the canonical textbook advantage credited to TTL is speed relative to early CMOS generations. Step-by-Step Reasoning: Compare propagation delay: TTL typically shorter than early CMOS.Evaluate ESD: CMOS is generally more sensitive to ESD than TTL.Cost and availability vary by era and vendor; not inherent advantages.Therefore, “faster” is the classic advantage. Verification / Alternative check: Datasheets for legacy 74xx TTL versus 4000-series CMOS show notably lower propagation delays for TTL at 5 V with similar loads, consistent with this generalization. Why Other Options Are Wrong: Less expensive / more widely available depend on market and time period, not intrinsic technology. “Not sensitive to electrostatic discharge” is incorrect; CMOS is the family known for ESD sensitivity; claiming TTL’s nonsensitivity as its chief advantage is misleading in the context of the classic TTL-CMOS comparison. Common Pitfalls: Assuming today’s high-speed CMOS equals early CMOS; improvements do not change the classic comparison taught in fundamentals. Confusing noise margin (often better in CMOS) with speed (historically stronger for TTL). Final Answer: faster

Question 5

CMOS package types in practice Which packaging options are commonly available for CMOS logic ICs in standard product lines?

Accepted Answer

Introduction / Context: Integrated circuit packaging affects assembly method, prototyping approach, and thermal behavior. CMOS logic families have been produced for decades in both through-hole and surface-mount forms to suit diverse manufacturing flows. Given Data / Assumptions: DIP (Dual In-line Package) is through-hole; SOIC (Small-Outline IC) is surface-mount. We are considering common catalog offerings for CMOS logic. Specialized packages (TSSOP, QFN) also exist but are outside this question. Concept / Approach: Standard CMOS logic devices (e.g., 74HC/74HCT, CD4000 series) are widely available in DIP for breadboarding and education, and in SOIC for modern automated assembly. Thus, both packaging styles are typical and expected in inventory. Step-by-Step Reasoning: Check historical availability: CD4000 and 74HC families offered in DIP.Check SMD prevalence: SOIC versions of the same logic functions are mainstream.Therefore, the correct choice is “DIP and SOIC configurations.” Verification / Alternative check: Vendor parametric searches routinely list both DIP and SOIC variants for common logic gates and flip-flops, confirming dual availability. Why Other Options Are Wrong: DIP-only or SOIC-only artificially restricts what is widely available. “Neither” contradicts decades of CMOS packaging practice. Common Pitfalls: Assuming through-hole is obsolete; while less common in mass production, DIP remains common in labs and education. Ignoring that many pin-compatible parts exist across multiple packages. Final Answer: DIP and SOIC configurations

Question 6

Minimum functional blocks for generating specialized digital waveforms Which minimal set of building blocks is sufficient to create specialized waveforms used in digital control and sequencing circuits?

Accepted Answer

Introduction / Context: Digital control and sequencing commonly rely on periodic signals (clocks) and shaped waveforms (pulses, duty-cycle patterns). Identifying the minimal set of building blocks needed to generate such waveforms is a core design skill for counters, timers, and state machines. Given Data / Assumptions: A “clock oscillator” provides a stable periodic timing reference. “Repetitive waveform generator” can shape pulses: monostables, astables, or dedicated timer ICs. “Basic gates” provide combinational shaping, gating, and logic level control. Concept / Approach: At the minimum, you need timing (oscillator), shaping (repetitive waveform generator), and logic (basic gates) to synthesize a range of control waveforms. Specialized counters, like Johnson counters, are useful but not strictly necessary to meet the baseline requirement stated in the question. Step-by-Step Solution: Select a clock source for periodic timing.Use a repetitive waveform or pulse generator (e.g., 555 astable/monostable) to create pulse widths and duty cycles.Apply basic gates (AND/OR/NOT) to gate, combine, and route these pulses to produce the desired control sequence. Verification / Alternative check: A simple sequencer can be built from a clock, a monostable for pulse shaping, and logic to enable/disable outputs. More complex patterns can later add counters or shift registers, but they are beyond the “minimum requirement.” Why Other Options Are Wrong: Including a Johnson counter is helpful for multi-phase sequences but not minimal. “DeMorgan pulse generator” is not a standard block; De Morgan’s theorems are algebraic identities, not hardware modules. Adding extra blocks goes beyond the minimum set requested. Common Pitfalls: Assuming counters are always required; many waveform tasks only need timing and gating. Confusing synthesis tools (theory) with physical modules (oscillators, timers, gates). Final Answer: basic gates, a clock oscillator, and a repetitive waveform generator

Question 7

Instrument selection for timing verification Which instrument is designed to capture and display multiple digital signals so they can be compared against expected timing diagrams?

Accepted Answer

Introduction / Context: In digital debugging, engineers often compare actual system timing to expected timing diagrams. The correct instrument must sample many digital lines concurrently, decode timing relationships, and display them clearly for analysis. Given Data / Assumptions: We need to observe multiple digital channels at once. We want to compare against timing diagrams (setup, hold, pulse widths, sequence). Signals are primarily digital (logic levels) rather than analog spectra. Concept / Approach: A logic analyzer is built to monitor numerous digital lines simultaneously, trigger on complex conditions, and present timing/state waveforms. While oscilloscopes can view a few channels, logic analyzers scale to dozens or hundreds, facilitating bus and protocol analysis. Step-by-Step Reasoning: DMM measures scalar values (voltage, resistance, current) and is unsuitable for multi-channel timing.A spectrum analyzer displays frequency content, not multi-line logic timing.A frequency counter measures frequency or period of a single source.A logic analyzer samples many digital inputs and aligns them vs. time for comparison with timing diagrams—this matches the requirement. Verification / Alternative check: Modern logic analyzers offer protocol decoders (I²C, SPI, UART) and state/timing modes, confirming their role in validating timing behavior against specifications. Why Other Options Are Wrong: DMM: no time-correlated multi-channel capture. Spectrum analyzer: frequency domain, not logic timing. Frequency counter: single number readout, not multi-channel timing display. Common Pitfalls: Trying to force a 2- or 4-channel oscilloscope to do deep timing on wide buses; it quickly becomes insufficient. Confusing protocol analyzers (which decode serial data) with timing analyzers; logic analyzers often do both. Final Answer: logic analyzer

Question 8

Reading logic symbols — NAND output bubble On a NAND gate symbol, what does the small bubble at the output explicitly indicate about the output signal?

Accepted Answer

Introduction / Context: Schematic symbols carry meaning beyond pin placement. The small bubble (often called an inversion bubble) communicates active-LOW behavior or inversion at that node. Correctly interpreting this symbol prevents wiring mistakes in mixed-polarity designs. Given Data / Assumptions: Standard ANSI/IEC logic symbols are in use. A bubble on a gate output denotes logical inversion of that node. NAND is the inversion of AND. Concept / Approach: The NAND function is X = NOT(A * B). The symbol for a NAND gate is typically an AND gate shape with a bubble on the output, visually indicating the output is the complement of the internal AND function. Bubbles on inputs/outputs consistently denote inversion in logic symbols. Step-by-Step Reasoning: Identify the base shape: AND gate.Notice the output bubble: this adds a NOT to the output node.Hence the overall function is NAND, confirming that the bubble conveys inversion. Verification / Alternative check: Compare symbols: An AND gate without a bubble outputs A * B; adding a bubble makes it NOT(A * B). Similarly, an OR gate with an output bubble is a NOR gate (NOT(A + B)). The symbol convention is consistent across logic families. Why Other Options Are Wrong: Open collector is indicated in datasheets or by specific annotations, not by an inversion bubble. Tristate outputs are usually shown with an additional control input and sometimes special symbol markers; a bubble alone does not denote tristate. “none of the above” is incorrect because the bubble clearly denotes inversion. Common Pitfalls: Mistaking inversion bubbles for polarity dots of analog symbols; in digital logic they have a strict NOT meaning. Ignoring that bubbles on inputs imply active-LOW enable signals. Final Answer: The output is inverted.

Question 9

Logic gate identification by behavior Which logic gate produces a HIGH (logic 1) output when any one or more of its inputs is HIGH?

Accepted Answer

Introduction / Context: Understanding the basic input–output behaviors of logic gates is foundational in digital electronics. The OR gate is one of the primary building blocks used in control logic, condition detection, and combinational circuits. Knowing when its output goes HIGH helps you interpret truth tables and design or debug systems quickly. Given Data / Assumptions: The circuit uses positive logic (HIGH = 1, LOW = 0). Inputs are independent and can be either 0 or 1. No inversions (bubbles) are present on the symbol unless specified. Concept / Approach: The Boolean expression for an n-input OR gate is Y = A + B + ... . In Boolean algebra, the plus sign represents logical OR, not arithmetic addition. The output Y equals 1 if at least one input is 1, and equals 0 only if all inputs are 0. This maps directly to the truth table and the gate's symbol-based reasoning in schematics. Step-by-Step Solution: Write the function: Y = A + B + C (for three inputs; the idea generalizes).Evaluate cases: if any input is 1, Y = 1; only A = B = C = 0 gives Y = 0.Match to the option that states this behavior: the OR gate. Verification / Alternative check: Create a quick truth table for two or three inputs. Count the rows with at least one HIGH; those rows yield Y = 1. This confirms the OR gate produces a HIGH for any input being HIGH. Simulation in a logic tool or quick breadboard test will show identical results. Why Other Options Are Wrong: AND gate outputs HIGH only when all inputs are HIGH. NOR gate is the inverse of OR; it is HIGH only when all inputs are LOW. NOT operation has a single input and outputs the complement. XOR outputs HIGH only when an odd number of inputs are HIGH, not merely any one. Common Pitfalls: Confusing Boolean + with arithmetic addition. In Boolean algebra, 1 + 1 = 1. Mixing OR with XOR when multiple inputs are HIGH. Final Answer: OR gate

Question 10

Truth table size for a 4-input NAND gate How many rows (input combinations) are required in the truth table of a four-input NAND gate?

Accepted Answer

Introduction / Context: Truth tables enumerate every possible input combination for a logic function. Knowing how many rows are required allows designers to plan verification efforts and to reason about complexity in combinational logic design. Given Data / Assumptions: Gate type: NAND. Number of inputs: 4 (A, B, C, D). Binary logic levels (each input is 0 or 1). Concept / Approach: The count of input combinations for an n-input logic function equals 2^n. This is independent of the gate type (AND, OR, NAND, NOR, etc.) because it depends only on the number of inputs and the binary nature of each input variable. Step-by-Step Solution: Identify n: here n = 4.Compute combinations: 2^n = 2^4 = 16.Therefore, the truth table requires 16 rows to cover all input patterns. Verification / Alternative check: List the inputs in binary counting order from 0000 to 1111; you will enumerate exactly 16 unique rows. Regardless of the gate's function, this exhaustive list is the complete set of input possibilities for four binary variables. Why Other Options Are Wrong: 2 and 4 correspond to 1- or 2-input functions, not 4 inputs. 8 corresponds to 2^3, the count for 3 inputs. 32 corresponds to 2^5, the count for 5 inputs. Common Pitfalls: Confusing the number of truth table rows with the number of gates used. Thinking gate type affects row count; it does not. Final Answer: 16

Question 11

Identifying a gate from inhibit behavior If a signal passing through a gate is inhibited by applying a LOW to one input, yet the output remains HIGH, the gate is which type?

Accepted Answer

Introduction / Context: Many digital designs use gating or enabling signals. Recognizing how a gate reacts when an input is forced LOW helps identify the gate from observed behavior and is valuable for troubleshooting with a logic probe or oscilloscope. Given Data / Assumptions: An input is driven LOW to inhibit a signal path. The observed output under this condition is HIGH. Positive logic is assumed (LOW = 0, HIGH = 1). Concept / Approach: NAND is the inversion of AND: Y = (A · B · ... )’. An AND gate forced with any LOW input yields 0 at its output. Inversion by NAND flips that to 1. Therefore, whenever any input is 0, a NAND gate outputs 1. Only when all inputs are 1 does a NAND output 0. This matches the stated inhibit behavior with a HIGH output result. Step-by-Step Solution: Model with two inputs: Y = (A · B)’.Set B = 0 (inhibit). Then A · 0 = 0 and Y = 0’ = 1.Thus the gate that remains HIGH when a single input is forced LOW is the NAND gate. Verification / Alternative check: Create a brief truth table for NAND. You will find that any row containing a 0 produces Y = 1, confirming the observation made in the problem statement. Why Other Options Are Wrong: AND would output LOW when any input is LOW. NOR outputs HIGH only when all inputs are LOW, not merely one. OR outputs LOW only when all inputs are LOW; otherwise it is HIGH but does not match the inhibit description. XOR depends on odd parity of HIGH inputs, not a general inhibit behavior. Common Pitfalls: Confusing NAND with NOR. Remember: NAND needs all inputs HIGH to go LOW. Final Answer: NAND

Question 12

NAND gate output condition for LOW Under which input condition does a NAND gate produce a LOW output?

Accepted Answer

Introduction / Context: NAND gates are universal components used widely because any logic function can be synthesized from NANDs. Knowing exactly when a NAND output falls LOW helps when designing active-low enables, resets, and interlock logic. Given Data / Assumptions: Positive logic and ideal gates. Two or more inputs may be present; the rule is the same. No additional inversion bubbles on the symbol. Concept / Approach: The NAND function is the logical AND followed by inversion: Y = (A · B · ... )’. The product A · B · ... equals 1 only when every input is 1. Inverting that product gives 0 only in that single all-HIGH condition; in every other case (at least one input 0), the output remains 1 (HIGH). Step-by-Step Solution: Write expression: Y = (A · B · C · ... )’.Case all inputs HIGH: the product is 1; inversion yields Y = 0.Any input LOW: the product is 0; inversion yields Y = 1. Verification / Alternative check: Construct a small truth table for two or three inputs. Check the single row with all 1s; there Y is 0. All other rows give Y = 1. This confirms the rule for NAND outputs. Why Other Options Are Wrong: “All inputs LOW” makes an AND product 0, which inverts to 1 at NAND output. “Any input LOW” similarly keeps the NAND output HIGH. “Any input HIGH” does not guarantee all inputs HIGH, so NAND stays HIGH unless all are HIGH. Toggling or clocking is irrelevant to combinational NAND behavior. Common Pitfalls: Mixing up NAND and NOR. NAND goes LOW only when all inputs are HIGH; NOR goes HIGH only when all inputs are LOW. Final Answer: all inputs are HIGH

Question 13

Identifying the gate with LOW output when any input is 0 Which gate always produces a LOW output for any case where one or more inputs are zero?

Accepted Answer

Introduction / Context: AND gates implement logical multiplication. In design practice, they are commonly used as enables that require all conditions to be true simultaneously. Recognizing the defining behavior of an AND gate helps when translating Boolean expressions into hardware and validating designs against truth tables. Given Data / Assumptions: Positive logic is used (1 = HIGH, 0 = LOW). Two or more inputs may feed the gate. Ideal gate with no timing hazards. Concept / Approach: The Boolean expression for an AND gate is Y = A · B · C · ... . A product evaluates to 1 only if every factor equals 1. If any input is 0, the product is 0, so the output must be LOW. This single rule fully defines the AND function across all input combinations. Step-by-Step Solution: Write Y = A · B · ... for the input set.Insert any 0 among the inputs: the product immediately becomes 0.Conclude that the output is LOW whenever one or more inputs are zero. Verification / Alternative check: Create a truth table for two or three inputs to visualize. The only row that yields HIGH is the row where all inputs are 1. Every other row includes at least one 0 and therefore produces 0 at the output, validating the definition of AND. Why Other Options Are Wrong: OR gate outputs 1 if any input is 1; it does not guarantee a LOW whenever an input is 0. NOT gate has a single input and simply complements it. NOR is OR followed by inversion; its behavior is different and depends on all inputs being 0 to produce a HIGH. XOR outputs HIGH when an odd number of inputs are HIGH; it is not defined by the stated condition. Common Pitfalls: Confusing AND with NAND. NAND outputs HIGH unless all inputs are HIGH. Final Answer: AND gate

Question 14

Digital logic concept check — structure of a NAND gate: Evaluate the statement: “A NAND gate is constructed by connecting an AND gate and an OR gate in series.” State whether this is accurate in standard Boolean logic hardware.

Accepted Answer

Introduction / Context: NAND is one of the four fundamental logic operations used to build digital systems. Understanding how a NAND gate relates to basic operations like AND, OR, and NOT helps students correctly interpret truth tables, simplify expressions, and analyze gate-level schematics. The prompt tests whether a learner knows the functional composition that defines a NAND gate. Given Data / Assumptions: The claim is that a NAND gate equals an AND gate placed in series with an OR gate. We assume two-input gates, positive logic, and standard Boolean behavior. “Connected in series” is interpreted as cascading the output of one gate into the input of another. Concept / Approach: By definition, NAND is the logical complement of AND. Symbolically, NAND(A,B) = NOT(AND(A,B)). This means the canonical construction is an AND gate followed by a NOT (inverter). There is no OR operation in the basic definition. Using OR would change the truth table and produce a different function altogether (e.g., an AND followed by OR with some other signal is not a NAND). Step-by-Step Solution: Write the target function: NAND(A,B) = (A * B)′.Realize that this equals NOT applied to the output of an AND gate.Compare with the claim “AND followed by OR”: OR is not an inversion; it changes logic, not complements it.Conclude the claim is inaccurate; the correct series pair is AND then NOT. Verification / Alternative check: Truth table check: AND(1,1)=1, all else 0. NAND is the opposite: outputs 0 only when both inputs are 1. Cascading an AND into an inverter reproduces that exactly; inserting an OR cannot produce this behavior without extra inputs or inversion. Why Other Options Are Wrong: Correct: Conflicts with the formal definition of NAND. Wired-logic TTL / CMOS pass-transistor logic / delay dependent: Implementation style or timing does not redefine the Boolean function. Common Pitfalls: Confusing the structural implementation (transistor networks) with the functional composition; forgetting that NAND = AND + NOT, nor AND + OR. Final Answer: Incorrect

Question 15

Gate identity check — is XNOR simply OR followed by inversion? Consider the statement: “An exclusive-NOR (XNOR) gate is an OR gate followed by a NOT gate.” Decide if this description is valid for standard two-input logic.

Accepted Answer

Introduction / Context: XNOR (exclusive-NOR) is the logical equality function: its output is 1 when the inputs are the same and 0 when they differ. Misidentifying XNOR as a simple OR followed by NOT is a common mistake that leads to incorrect truth tables and design errors in parity checking and comparator circuits. Given Data / Assumptions: Two-input logic in positive logic convention. “OR followed by NOT” means output = NOT(OR(A,B)) = NOR(A,B). We compare NOR with XNOR behavior. Concept / Approach: Define functions explicitly: XNOR(A,B) = (A AND B) OR (A′ AND B′). NOR(A,B) = NOT(A OR B) = A′ AND B′. NOR is true only when both inputs are 0. XNOR is true when A=B, i.e., for pairs (0,0) and (1,1). Because XNOR also outputs 1 for (1,1), it cannot be realized by a single OR followed by NOT. Step-by-Step Solution: List XNOR truth table: 00→1, 01→0, 10→0, 11→1.List NOR truth table: 00→1, 01→0, 10→0, 11→0.Compare rows: XNOR(11)=1 but NOR(11)=0, so they differ.Therefore, “OR then NOT” is NOR, not XNOR; the statement is incorrect. Verification / Alternative check: Implement XNOR as NOT(XOR(A,B)) or as (A AND B) OR (A′ AND B′). Both implementations yield equality logic, not NOR. Why Other Options Are Wrong: Correct / mutually exclusive inputs / wired-OR / De Morgan: None transform OR+NOT into XNOR for all input pairs. Common Pitfalls: Equating “NOR” and “XNOR” due to the “N” prefix; assuming any gate followed by NOT simply adds an “X.” Only XOR + NOT becomes XNOR. Final Answer: Incorrect

Question 16

Identify the gate by its behavior: “Output is OFF (0) when inputs are the same, and ON (1) when inputs are different.” Which standard gate matches this description?

Accepted Answer

Introduction / Context: Recognizing a logic function from a verbal description is a core digital skill. The statement describes a detector that turns ON only when inputs differ. This behavior underpins parity generation, error checking, and bit-wise comparison operations in CPUs and communication systems. Given Data / Assumptions: Two-input gate, positive logic. “ON” maps to logic 1, “OFF” maps to logic 0. Inputs are binary values A and B. Concept / Approach: The exclusive-OR (XOR) gate outputs 1 only when exactly one input is 1; equivalently, when inputs differ. Its complement, XNOR, outputs 1 when inputs are equal. AND/NOR/Buffer do not show this “difference detection” behavior. Therefore, the verbal rule exactly matches XOR. Step-by-Step Solution: Write XOR truth rule: XOR(A,B)=1 if (A,B) is 01 or 10; else 0.Map “inputs the same” → 00 or 11 → XOR=0.Map “inputs different” → 01 or 10 → XOR=1.Hence the gate is Exclusive-OR (XOR). Verification / Alternative check: Algebraic form: XOR(A,B) = A′B + AB′. This is true when exactly one term is true, i.e., inputs differ. Hardware libraries list XOR as a “difference” or “parity” gate, confirming the match. Why Other Options Are Wrong: Exclusive-NOR (XNOR): Outputs 1 when inputs are the same, opposite of the description. AND: Requires both inputs 1; ignores equality/inequality cases. NOR: Outputs 1 only for 00; not a difference detector. Buffer: Copies a single input; does not combine two inputs. Common Pitfalls: Confusing XOR and XNOR due to similar naming; forgetting that XOR highlights differences while XNOR highlights equality. Final Answer: Exclusive-OR (XOR)

Question 17

Core XOR property — outputs 1 only when inputs differ: Confirm or reject the statement: “For a two-input XOR gate, the output is 1 only when the inputs are different.”

Accepted Answer

Introduction / Context: The exclusive-OR (XOR) gate is central to parity bits, adders (sum without carry), and data encryption primitives because it toggles output when inputs differ. This question checks the canonical verbal definition against the truth table everyone should know. Given Data / Assumptions: Two inputs A and B, positive logic. We test the rule “output is 1 only when inputs are different.” No timing or analog behavior considered; pure Boolean function. Concept / Approach: XOR may be written as A ⊕ B = A′B + AB′. This sum of products turns true exactly for the input pairs 01 and 10 and false for 00 and 11. Thus the statement matches the formal expression and the standard truth table. Step-by-Step Solution: List cases: 00→0; 01→1; 10→1; 11→0.Identify “different” pairs: 01 and 10, where XOR=1.Identify “same” pairs: 00 and 11, where XOR=0.Therefore, the statement is correct. Verification / Alternative check: View XOR as inequality comparator: output = 1 if A ≠ B. In digital comparators, equality output is often implemented as XNOR because XNOR=1 when A=B. This duality verifies the rule by complement. Why Other Options Are Wrong: Incorrect: Contradicts the truth table. Negative logic / complementary only / fan-out dependent: Choosing active-low conventions or drive capacity does not change the Boolean truth table. Common Pitfalls: Confusing XOR with OR (which is true for 11 as well) or with XNOR (true when inputs are equal). Always anchor to the 4-row truth table to avoid mix-ups. Final Answer: Correct

Question 18

Clarity of terminology — do logic gates “open their outputs,” or do they deterministically compute outputs? Evaluate the statement: “Logic gate circuits contain predictable gate functions that open their outputs.”

Accepted Answer

Introduction / Context: Digital logic gates are deterministic Boolean operators. Their outputs are computed from inputs according to fixed truth tables. The phrase “open their outputs” confuses this function with special output structures (like open-collector or tri-state) that can electrically disconnect a pin, which is different from computing 0 or 1. The prompt checks clarity between function and electrical drive mode. Given Data / Assumptions: Standard gates (AND, OR, NAND, etc.) with push-pull outputs unless otherwise specified. “Open their outputs” is interpreted as “leave the output floating,” which is not the general behavior. We focus on logical behavior, not specific I/O topologies. Concept / Approach: Logic gates implement predictable functions mapping inputs to outputs per a truth table. While some devices provide open-collector or tri-state options that can place the output in high-impedance (Hi-Z), that is a separate feature and not synonymous with the fundamental gate function. Therefore the wording in the statement is misleading and inaccurate in general form. Step-by-Step Solution: Identify the claim: gates “open their outputs.”Contrast with reality: gates compute outputs as 0/1; most use push-pull drivers.Acknowledge exceptions: open-collector/tri-state parts can float outputs, but this is not universal and not what “predictable gate functions” means.Conclude the statement is incorrect as written. Verification / Alternative check: Datasheets specify truth tables separately from output stage type (totem-pole, open-collector, tri-state). This separation proves that “opening” (Hi-Z) is an electrical mode, not the gate’s logical function. Why Other Options Are Wrong: Correct: Misstates the nature of gate operation. Tri-state / open-collector only: These are special cases; the blanket statement remains wrong. Asynchronous systems: Clocking style does not alter gate output semantics. Common Pitfalls: Conflating Boolean function with I/O topology; assuming “open” means logical 1 or 0 rather than Hi-Z. Keep logic behavior (truth tables) separate from electrical drive types. Final Answer: Incorrect

Question 19

Gate identification by requirement: “If both inputs must be ON (logic 1) for the output to be ON, which gate is described?” Determine whether the assertion correctly identifies an AND gate.

Accepted Answer

Introduction / Context: Being able to translate verbal behavior into a gate name enables quick schematic reading and functional reasoning. The classic description “output is 1 only when all inputs are 1” is the textbook definition of AND, used throughout digital design from enable signals to address decoding. Given Data / Assumptions: Two-input gates in positive logic. “ON” corresponds to logic 1. We ignore electrical nuances like thresholds and timing. Concept / Approach: AND implements multiplication of logic variables: Y = A * B. The output is high only for A=1 and B=1. For any input being 0, the product is 0. This matches the verbal requirement exactly and identifies the AND function unambiguously. Step-by-Step Solution: Write truth table: 00→0, 01→0, 10→0, 11→1.Interpret “both inputs must be 1”: only the 11 row produces 1.Map to gate: this is AND.Therefore, the assertion is correct. Verification / Alternative check: Boolean algebra: Y = A * B. De Morgan’s complement is NAND = (A * B)′, which flips the output for 11 only. This dual view reinforces the identification of AND from the verbal rule. Why Other Options Are Wrong: Incorrect: Conflicts with the canonical definition. Negative logic / Schmitt / delay: Logic polarity, hysteresis, or timing do not change the truth table of AND. Common Pitfalls: Confusing AND with OR (which is true for 11, 10, and 01). Remember: AND requires all inputs asserted; OR requires any input asserted. Final Answer: Correct

Question 20

NAND–AND relationship: Assess the claim: “The output of a NAND gate equals the inverted output of an AND gate.” Determine if this statement is accurate for standard positive logic.

Accepted Answer

Introduction / Context: NAND and AND are complementary operations. Many simplification techniques and universal-gate constructions rely on this exact relationship. Verifying the definition guards against common mistakes when reading mixed NAND/AND schematics or when replacing functions using universal NAND gates. Given Data / Assumptions: Positive logic, two inputs A and B. Standard Boolean semantics; no electrical edge cases considered. Concept / Approach: By definition, NAND(A,B) = NOT(AND(A,B)). In symbolic form: Y_NAND = (A * B)′. Therefore, if Y_AND = A * B, then Y_NAND = NOT(Y_AND). This matches the statement precisely and is true independent of implementation technology (TTL, CMOS, ECL). Step-by-Step Solution: Compute AND output: Y_AND = A * B.Invert it: Y = NOT(Y_AND).Recognize this equals NAND truth table (only 11 maps to 0, others to 1).Therefore, the claim is correct. Verification / Alternative check: Truth table confirms: AND: 00→0, 01→0, 10→0, 11→1. NAND is the complement: 00→1, 01→1, 10→1, 11→0, which is exactly the inversion of AND’s output row by row. Why Other Options Are Wrong: Incorrect or technology-limited options: Boolean identity does not depend on output topology or supply voltage; it is logically universal. Common Pitfalls: Mixing up NAND with NOR (the complement of OR). Remember: NAND complements AND; NOR complements OR. Final Answer: Correct

Logic Gates Questions