Question 1

Gate identification from behavior: A signal is inhibited by applying a LOW to one input, yet the output remains HIGH. Which logic gate matches this description?

Accepted Answer

Introduction / Context: Recognizing a gate from its qualitative behavior is a key digital logic skill. The description says a LOW on any input inhibits the signal but produces a HIGH output regardless of the other inputs. This strongly hints at the inversion of an AND function, which is the NAND gate. Given Data / Assumptions: At least two-input logic gate. Driving one input LOW forces the output to a known state. Observed output is HIGH when any single input is LOW. Concept / Approach: The NAND truth function is Y = NOT(A * B * …). For NAND, the output is LOW only when all inputs are HIGH. If any input is LOW, the product A * B * … equals 0, so NOT(0) = 1 → output HIGH. Hence a LOW on an input 'inhibits' the low-output condition and produces HIGH, matching the description. Step-by-Step Solution: For NAND: if any input = 0 → product = 0 → output = 1.Therefore a LOW input guarantees a HIGH output (signal inhibited).Only when all inputs are 1 is the output 0. Verification / Alternative check: Compare to AND: any LOW makes output LOW (contradicts the statement). Compare to OR: any HIGH makes HIGH (doesn’t mention LOW causing HIGH). Compare to NOR: any HIGH causes LOW (opposite behavior). Thus only NAND fits. Why Other Options Are Wrong: AND: Any LOW → output LOW, not HIGH. NOR: Any HIGH → output LOW, opposite behavior. OR: Any HIGH → output HIGH; the described trigger is a LOW input. Common Pitfalls: Confusing NAND with NOR; remember NAND inverts AND (only all HIGH gives LOW), while NOR inverts OR (any HIGH gives LOW). Final Answer: NAND

Question 2

74xx logic families: How many independent 2-input NAND gates are contained inside a standard 7400 TTL IC (often called a “quad NAND”)?

Accepted Answer

Introduction / Context: The 7400-series TTL family is a cornerstone of digital electronics. Part numbers encode both function and quantity. The 7400 device is a classic example, widely used in education and industry for simple logic building blocks. Given Data / Assumptions: Device: 7400 TTL logic IC. Function: 2-input NAND gates packaged together. Package: 14-pin DIP in many versions. Concept / Approach: The 7400 is known as a 'quad 2-input NAND'. 'Quad' indicates four independent gates in one package. Pinouts show inputs and outputs mapped to four separate NAND sections, with Vcc and GND on standard pins (e.g., 14 and 7 in DIP packages). Step-by-Step Solution: Identify the family code: 7400.Recall canonical name: quad 2-input NAND.Therefore, the IC contains 4 NAND gates. Verification / Alternative check: Compare to related devices: 7402 is quad 2-input NOR, 7404 is hex inverter (6 NOT gates), 7408 is quad 2-input AND. The pattern corroborates the 7400 having four NANDs. Why Other Options Are Wrong: 1 or 2: Would be 'single' or 'dual,' not 7400. 8: That would be 'octal' and would not match pin constraints of a 14-pin DIP for 2-input gates. Common Pitfalls: Confusing 7400 with 7404 (hex inverters) or with CMOS 4000-series numbering. Always confirm the family and function from the part number. Final Answer: 4

Question 3

Truth table size: For a four-input logic circuit (4 independent binary inputs), how many rows/entries are required in the complete truth table?

Accepted Answer

Introduction / Context: Truth tables enumerate all possible input combinations and the resulting output(s). The size grows exponentially with the number of inputs, a key reason minimization tools (like Karnaugh maps or Boolean algebra) are important for larger systems. Given Data / Assumptions: Number of inputs n = 4. Each input is binary (0 or 1). We seek the number of unique rows in the truth table. Concept / Approach: For n binary variables, the number of distinct combinations is 2^n. Each combination corresponds to one row of the truth table. Thus, for four inputs, the table must have 2^4 entries covering all permutations from 0000 to 1111. Step-by-Step Solution: Let n = 4.Compute 2^n = 2^4.2^4 = 16 unique input combinations → 16 rows. Verification / Alternative check: List a subset to verify: 0000, 0001, 0010, …, 1111. Counting from 0 to 15 in binary gives exactly 16 combinations, confirming the result. Why Other Options Are Wrong: 4 or 8 or 12: Do not equal 2^4; they miss some combinations and would yield an incomplete truth table. Common Pitfalls: Confusing the number of inputs with the number of outputs or forgetting the exponential growth rule 2^n. This error leads to incomplete testing in design and verification. Final Answer: 16

Question 4

Characterizing NAND behavior: Which statement best describes a NAND gate's input–output relationship for the case of LOW inputs?

Accepted Answer

Introduction / Context: NAND is a universal logic gate. Understanding its behavior for edge cases (all inputs LOW vs. all inputs HIGH) helps quickly predict outcomes and design with minimal gates. Here, the focus is on the output when inputs are LOW. Given Data / Assumptions: Two-input NAND gate for simplicity (the conclusion generalizes). Logic levels: LOW = 0, HIGH = 1. Concept / Approach: NAND is the inversion of AND. The AND of two LOWs is 0, and then inverting yields 1. Therefore, with (0, 0) applied to a NAND, the output is HIGH. In general, NAND gives LOW only when all inputs are HIGH; for any other combination (including all LOW), it outputs HIGH. Step-by-Step Solution: For inputs A = 0, B = 0 → AND: 0 * 0 = 0.NAND output Y = NOT(0) = 1.Hence: LOW inputs → HIGH output. Verification / Alternative check: Quick truth table check: (0,0)→1; (0,1)→1; (1,0)→1; (1,1)→0. Only the all-HIGH case creates a LOW output, consistent with the rule of NAND. Why Other Options Are Wrong: LOW inputs and a LOW output: That is the AND behavior, not NAND. HIGH inputs and a HIGH output: NAND of (1,1) is 0, not 1. None of these: One option is correct as shown. Common Pitfalls: Mixing AND and NAND logic; forgetting that NAND inverts the AND result. Also watch ambiguous phrasing—always compute with simple cases to confirm intuition. Final Answer: LOW inputs and a HIGH output

Question 5

Identify the gate that outputs the complement of its single input (i.e., logical inversion): Which basic logic gate performs this operation?

Accepted Answer

Introduction / Context: Digital systems often need the logical complement of a signal for control, timing, and active-low conventions. The device that provides this complement is fundamental and appears in virtually every logic family and integrated function block. Given Data / Assumptions: Single-input, single-output logic function. Output equals NOT(input). Ideal logic levels are assumed. Concept / Approach: The NOT operation maps 0 → 1 and 1 → 0. The simplest gate implementing NOT is called an inverter (sometimes labeled as a NOT gate or 7404 in TTL for a hex inverter). It is distinct from comparators, which are analog-level thresholding devices that produce logic-level outputs but are not simple NOT functions of a single logic input. Step-by-Step Solution: Define the function: Y = NOT(X).Recognize device name: inverter (NOT gate).Select ”INVERTER gate.” Verification / Alternative check: Truth table for an inverter: X=0 → Y=1; X=1 → Y=0. Other gates (AND, OR) require two or more inputs and do not invert a single input by themselves. Why Other Options Are Wrong: OR / AND: Multi-input gates that do not invert a single input. Comparator: Analog threshold device; output depends on analog difference relative to a reference, not merely the logical complement of a logic input. Common Pitfalls: Assuming a comparator is a digital NOT because it outputs logic levels—its function and use cases are different (windowing, thresholding, Schmitt triggering). Final Answer: INVERTER gate

Question 6

Realizing XOR from basic gates: Exclusive-OR (XOR) gates can be implemented using which combination of fundamental logic gates?

Accepted Answer

Introduction / Context: Many digital designs restrict the primitive gate set to AND, OR, and NOT (or to NAND/NOR). Being able to build XOR from these primitives is essential because XOR underlies adders, parity generators, and data comparison logic. Given Data / Assumptions: XOR two-input definition: output HIGH if inputs differ (01 or 10) and LOW if inputs are the same (00 or 11). Available primitives: AND, OR, NOT. Concept / Approach: One canonical realization is: XOR = (A * NOT B) + (NOT A * B). This uses two AND gates and two NOT gates feeding an OR gate. It exactly captures the “one or the other but not both” behavior of XOR. Step-by-Step Solution: Compute term1 = A * NOT B.Compute term2 = NOT A * B.XOR output Y = term1 + term2. Verification / Alternative check: Truth table check: For A,B = 00 → Y=0; 01 → Y=1; 10 → Y=1; 11 → Y=0. This matches XOR. Alternative forms exist using only NAND or only NOR, but they still conceptually reduce to combinations of AND/OR/NOT operations. Why Other Options Are Wrong: OR only: Cannot suppress the 11 case to 0. AND + NOT only or OR + NOT only: Insufficient to generate both terms and combine correctly without all three primitives in the canonical form. Common Pitfalls: Confusing XOR with inclusive OR; XOR excludes the 11 case. Also, forgetting to invert one input per product term yields the wrong function. Final Answer: AND gates, OR gates, and NOT gates

Question 7

Minimal transistor implementation: A single bipolar junction transistor (BJT) stage can be wired to implement which basic digital logic gate?

Accepted Answer

Introduction / Context: At the lowest level, logic gates are built from transistors and resistors. Understanding what a single transistor can realize helps in appreciating how complex logic functions are composed and why certain gates are considered universal only when more devices are used. Given Data / Assumptions: Single active device (one BJT) with resistive biasing. Digital operation (saturation/cutoff for switching or small-signal inversion for logic-level inversion). Standard positive logic conventions. Concept / Approach: A common-emitter BJT stage provides inversion: a HIGH input drives the transistor into conduction and pulls the output LOW; a LOW input turns it off, allowing the pull-up to produce a HIGH output. Thus, a single BJT can act as a NOT gate (inverter). Creating AND, OR, NAND typically requires multiple transistors or diode-resistor networks with transistor inversion. Step-by-Step Solution: Choose topology: common-emitter with collector resistor and input base drive.Input HIGH → base current flows → transistor saturates → collector LOW.Input LOW → transistor off → collector pulled HIGH → inversion achieved. Verification / Alternative check: Many TTL inverters (e.g., one section of a 7404 die) boil down to a single transistor stage performing inversion, often augmented by additional devices for noise margins and current drive. The core function, however, is inversion using one active device. Why Other Options Are Wrong: AND / OR: Require combining multiple inputs; at least two active paths are needed. NAND: Although NAND can be made from series/parallel transistor networks, it still needs more than one active device to handle multiple inputs. Common Pitfalls: Assuming a diode-resistor network alone can implement robust logic levels with good noise margins—it typically needs a transistor stage for restoration and inversion. Final Answer: NOT gates

Question 8

OR gate behavior (any-true condition): Which logic gate outputs a HIGH (logic “1”) when any one of its inputs is HIGH?

Accepted Answer

Introduction / Context: Recognizing the canonical behavior of the OR gate is essential for control logic, enabling conditions, and combining multiple event signals. The key phrase is “any one input HIGH” causes the output to be HIGH, which defines the inclusive OR operation. Given Data / Assumptions: Standard positive logic levels (0 = LOW, 1 = HIGH). Two or more inputs (the rule generalizes to N inputs). Concept / Approach: The inclusive OR function is defined by Y = A + B + … . The output is LOW only when all inputs are LOW. If any single input is HIGH, the sum evaluates to 1 and the output becomes HIGH. This is distinct from XOR, which is HIGH only when an odd number of inputs are HIGH, and from NOR, which outputs the complement of OR. Step-by-Step Solution: Evaluate OR for typical cases: (0,0) → 0; (1,0) → 1; (0,1) → 1; (1,1) → 1.Generalize: if any input = 1 → output = 1.Identify the gate that matches: OR gate. Verification / Alternative check: Truth table or Boolean algebra confirms that only the all-zero input combination yields a zero output. Hardware implementations in TTL/CMOS families (e.g., 7432 for OR) behave accordingly. Why Other Options Are Wrong: AND: Requires all inputs HIGH for a HIGH output. NOR: Produces LOW when any input is HIGH (the inverse of OR). NOT: Single-input inverter; does not implement multi-input any-true logic. Common Pitfalls: Confusing OR with XOR; remember inclusive OR allows multiple HIGH inputs without forcing the output LOW. Final Answer: OR gate

Question 9

AND logic gate behavior In digital electronics, under what input condition(s) will a multi-input AND gate produce a HIGH (logic 1) at its output?

Accepted Answer

Introduction / Context: An AND gate is one of the fundamental combinational logic elements used in digital systems, microcontrollers, and FPGA designs. Knowing precisely when its output goes HIGH is essential for designing control logic, enabling conditions, and safety interlocks. Given Data / Assumptions: Standard positive logic convention is used (HIGH = logic 1, LOW = logic 0). The gate may have two or more inputs. Ideal logic levels with sufficient noise margins. Concept / Approach: The truth table of an AND function is defined by the Boolean expression Y = A * B * C * …, where * denotes the logical AND operation. The product of logic variables equals 1 only if every factor equals 1. Hence, the AND gate outputs a 1 precisely when every input is 1. Step-by-Step Solution: Define the function: Y = A1 * A2 * … * An.Evaluate case when any input is 0: since 0 * X = 0, the output is 0.Evaluate case when all inputs are 1: since 1 * 1 * … * 1 = 1, the output is 1.Therefore, a HIGH output occurs only when all inputs are HIGH. Verification / Alternative check: Construct a truth table for a 3-input AND gate and observe that the sole HIGH output row is A = 1, B = 1, C = 1. Karnaugh mapping also yields a single minterm representing the all-ones input. Why Other Options Are Wrong: At least one input is HIGH: describes OR behavior, not AND.At least one input is LOW: this guarantees a LOW output for AND, not HIGH.All inputs are LOW: AND of zeros is zero. Common Pitfalls: Confusing AND with OR, or mixing negative logic conventions. Also, assuming a floating input acts like a logic 1—floating inputs must be properly biased; otherwise, output can be unpredictable. Final Answer: All inputs are HIGH.

Question 10

Identifying the gate with LOW output when any input is zero In positive-logic digital circuits, which gate outputs a LOW whenever one or more inputs are logic 0?

Accepted Answer

Introduction / Context: Selecting the correct logic gate is a foundational skill in digital design. This question targets recognition of the gate whose output immediately drops LOW if any input is LOW. Given Data / Assumptions: Positive logic (HIGH = 1, LOW = 0). Ideal gate behavior (ignoring propagation delay and noise for the concept). Two or more inputs possible. Concept / Approach: The AND gate is defined by Y = A * B * C * … . In Boolean algebra, the product is 1 only if every factor equals 1. Consequently, if any input is 0, the product becomes 0 and the output is LOW. This directly matches the description. Step-by-Step Solution: Write the Boolean function: Y = A1 * A2 * … * An.Consider any single input Ai = 0: Y = 0 * (rest) = 0.Thus, for any input at 0, the output is forced LOW.Therefore, the described gate behavior belongs to AND. Verification / Alternative check: Truth table for a 2-input AND shows outputs 1 only for (1,1); all other combinations with a 0 produce 0. Extending to more inputs preserves this rule. Why Other Options Are Wrong: OR gate: outputs 1 if any input is 1; contradicts the prompt.NOT gate: single-input inverter; behavior not described by multiple inputs.NAND gate: outputs LOW only when all inputs are 1; not when any input is 0. Common Pitfalls: Confusing NAND with AND because both are related; remember NAND is the complement of AND and is HIGH whenever any input is 0. Final Answer: AND gate

Question 11

Digital logic concept check — structure of a NAND gate: Evaluate the statement: “A NAND gate is constructed by connecting an AND gate and an OR gate in series.” State whether this is accurate in standard Boolean logic hardware.

Accepted Answer

Introduction / Context: NAND is one of the four fundamental logic operations used to build digital systems. Understanding how a NAND gate relates to basic operations like AND, OR, and NOT helps students correctly interpret truth tables, simplify expressions, and analyze gate-level schematics. The prompt tests whether a learner knows the functional composition that defines a NAND gate. Given Data / Assumptions: The claim is that a NAND gate equals an AND gate placed in series with an OR gate. We assume two-input gates, positive logic, and standard Boolean behavior. “Connected in series” is interpreted as cascading the output of one gate into the input of another. Concept / Approach: By definition, NAND is the logical complement of AND. Symbolically, NAND(A,B) = NOT(AND(A,B)). This means the canonical construction is an AND gate followed by a NOT (inverter). There is no OR operation in the basic definition. Using OR would change the truth table and produce a different function altogether (e.g., an AND followed by OR with some other signal is not a NAND). Step-by-Step Solution: Write the target function: NAND(A,B) = (A * B)′.Realize that this equals NOT applied to the output of an AND gate.Compare with the claim “AND followed by OR”: OR is not an inversion; it changes logic, not complements it.Conclude the claim is inaccurate; the correct series pair is AND then NOT. Verification / Alternative check: Truth table check: AND(1,1)=1, all else 0. NAND is the opposite: outputs 0 only when both inputs are 1. Cascading an AND into an inverter reproduces that exactly; inserting an OR cannot produce this behavior without extra inputs or inversion. Why Other Options Are Wrong: Correct: Conflicts with the formal definition of NAND. Wired-logic TTL / CMOS pass-transistor logic / delay dependent: Implementation style or timing does not redefine the Boolean function. Common Pitfalls: Confusing the structural implementation (transistor networks) with the functional composition; forgetting that NAND = AND + NOT, nor AND + OR. Final Answer: Incorrect

Question 12

Gate identity check — is XNOR simply OR followed by inversion? Consider the statement: “An exclusive-NOR (XNOR) gate is an OR gate followed by a NOT gate.” Decide if this description is valid for standard two-input logic.

Accepted Answer

Introduction / Context: XNOR (exclusive-NOR) is the logical equality function: its output is 1 when the inputs are the same and 0 when they differ. Misidentifying XNOR as a simple OR followed by NOT is a common mistake that leads to incorrect truth tables and design errors in parity checking and comparator circuits. Given Data / Assumptions: Two-input logic in positive logic convention. “OR followed by NOT” means output = NOT(OR(A,B)) = NOR(A,B). We compare NOR with XNOR behavior. Concept / Approach: Define functions explicitly: XNOR(A,B) = (A AND B) OR (A′ AND B′). NOR(A,B) = NOT(A OR B) = A′ AND B′. NOR is true only when both inputs are 0. XNOR is true when A=B, i.e., for pairs (0,0) and (1,1). Because XNOR also outputs 1 for (1,1), it cannot be realized by a single OR followed by NOT. Step-by-Step Solution: List XNOR truth table: 00→1, 01→0, 10→0, 11→1.List NOR truth table: 00→1, 01→0, 10→0, 11→0.Compare rows: XNOR(11)=1 but NOR(11)=0, so they differ.Therefore, “OR then NOT” is NOR, not XNOR; the statement is incorrect. Verification / Alternative check: Implement XNOR as NOT(XOR(A,B)) or as (A AND B) OR (A′ AND B′). Both implementations yield equality logic, not NOR. Why Other Options Are Wrong: Correct / mutually exclusive inputs / wired-OR / De Morgan: None transform OR+NOT into XNOR for all input pairs. Common Pitfalls: Equating “NOR” and “XNOR” due to the “N” prefix; assuming any gate followed by NOT simply adds an “X.” Only XOR + NOT becomes XNOR. Final Answer: Incorrect

Question 13

Identify the gate by its behavior: “Output is OFF (0) when inputs are the same, and ON (1) when inputs are different.” Which standard gate matches this description?

Accepted Answer

Introduction / Context: Recognizing a logic function from a verbal description is a core digital skill. The statement describes a detector that turns ON only when inputs differ. This behavior underpins parity generation, error checking, and bit-wise comparison operations in CPUs and communication systems. Given Data / Assumptions: Two-input gate, positive logic. “ON” maps to logic 1, “OFF” maps to logic 0. Inputs are binary values A and B. Concept / Approach: The exclusive-OR (XOR) gate outputs 1 only when exactly one input is 1; equivalently, when inputs differ. Its complement, XNOR, outputs 1 when inputs are equal. AND/NOR/Buffer do not show this “difference detection” behavior. Therefore, the verbal rule exactly matches XOR. Step-by-Step Solution: Write XOR truth rule: XOR(A,B)=1 if (A,B) is 01 or 10; else 0.Map “inputs the same” → 00 or 11 → XOR=0.Map “inputs different” → 01 or 10 → XOR=1.Hence the gate is Exclusive-OR (XOR). Verification / Alternative check: Algebraic form: XOR(A,B) = A′B + AB′. This is true when exactly one term is true, i.e., inputs differ. Hardware libraries list XOR as a “difference” or “parity” gate, confirming the match. Why Other Options Are Wrong: Exclusive-NOR (XNOR): Outputs 1 when inputs are the same, opposite of the description. AND: Requires both inputs 1; ignores equality/inequality cases. NOR: Outputs 1 only for 00; not a difference detector. Buffer: Copies a single input; does not combine two inputs. Common Pitfalls: Confusing XOR and XNOR due to similar naming; forgetting that XOR highlights differences while XNOR highlights equality. Final Answer: Exclusive-OR (XOR)

Question 14

Core XOR property — outputs 1 only when inputs differ: Confirm or reject the statement: “For a two-input XOR gate, the output is 1 only when the inputs are different.”

Accepted Answer

Introduction / Context: The exclusive-OR (XOR) gate is central to parity bits, adders (sum without carry), and data encryption primitives because it toggles output when inputs differ. This question checks the canonical verbal definition against the truth table everyone should know. Given Data / Assumptions: Two inputs A and B, positive logic. We test the rule “output is 1 only when inputs are different.” No timing or analog behavior considered; pure Boolean function. Concept / Approach: XOR may be written as A ⊕ B = A′B + AB′. This sum of products turns true exactly for the input pairs 01 and 10 and false for 00 and 11. Thus the statement matches the formal expression and the standard truth table. Step-by-Step Solution: List cases: 00→0; 01→1; 10→1; 11→0.Identify “different” pairs: 01 and 10, where XOR=1.Identify “same” pairs: 00 and 11, where XOR=0.Therefore, the statement is correct. Verification / Alternative check: View XOR as inequality comparator: output = 1 if A ≠ B. In digital comparators, equality output is often implemented as XNOR because XNOR=1 when A=B. This duality verifies the rule by complement. Why Other Options Are Wrong: Incorrect: Contradicts the truth table. Negative logic / complementary only / fan-out dependent: Choosing active-low conventions or drive capacity does not change the Boolean truth table. Common Pitfalls: Confusing XOR with OR (which is true for 11 as well) or with XNOR (true when inputs are equal). Always anchor to the 4-row truth table to avoid mix-ups. Final Answer: Correct

Question 15

Clarity of terminology — do logic gates “open their outputs,” or do they deterministically compute outputs? Evaluate the statement: “Logic gate circuits contain predictable gate functions that open their outputs.”

Accepted Answer

Introduction / Context: Digital logic gates are deterministic Boolean operators. Their outputs are computed from inputs according to fixed truth tables. The phrase “open their outputs” confuses this function with special output structures (like open-collector or tri-state) that can electrically disconnect a pin, which is different from computing 0 or 1. The prompt checks clarity between function and electrical drive mode. Given Data / Assumptions: Standard gates (AND, OR, NAND, etc.) with push-pull outputs unless otherwise specified. “Open their outputs” is interpreted as “leave the output floating,” which is not the general behavior. We focus on logical behavior, not specific I/O topologies. Concept / Approach: Logic gates implement predictable functions mapping inputs to outputs per a truth table. While some devices provide open-collector or tri-state options that can place the output in high-impedance (Hi-Z), that is a separate feature and not synonymous with the fundamental gate function. Therefore the wording in the statement is misleading and inaccurate in general form. Step-by-Step Solution: Identify the claim: gates “open their outputs.”Contrast with reality: gates compute outputs as 0/1; most use push-pull drivers.Acknowledge exceptions: open-collector/tri-state parts can float outputs, but this is not universal and not what “predictable gate functions” means.Conclude the statement is incorrect as written. Verification / Alternative check: Datasheets specify truth tables separately from output stage type (totem-pole, open-collector, tri-state). This separation proves that “opening” (Hi-Z) is an electrical mode, not the gate’s logical function. Why Other Options Are Wrong: Correct: Misstates the nature of gate operation. Tri-state / open-collector only: These are special cases; the blanket statement remains wrong. Asynchronous systems: Clocking style does not alter gate output semantics. Common Pitfalls: Conflating Boolean function with I/O topology; assuming “open” means logical 1 or 0 rather than Hi-Z. Keep logic behavior (truth tables) separate from electrical drive types. Final Answer: Incorrect

Question 16

Gate identification by requirement: “If both inputs must be ON (logic 1) for the output to be ON, which gate is described?” Determine whether the assertion correctly identifies an AND gate.

Accepted Answer

Introduction / Context: Being able to translate verbal behavior into a gate name enables quick schematic reading and functional reasoning. The classic description “output is 1 only when all inputs are 1” is the textbook definition of AND, used throughout digital design from enable signals to address decoding. Given Data / Assumptions: Two-input gates in positive logic. “ON” corresponds to logic 1. We ignore electrical nuances like thresholds and timing. Concept / Approach: AND implements multiplication of logic variables: Y = A * B. The output is high only for A=1 and B=1. For any input being 0, the product is 0. This matches the verbal requirement exactly and identifies the AND function unambiguously. Step-by-Step Solution: Write truth table: 00→0, 01→0, 10→0, 11→1.Interpret “both inputs must be 1”: only the 11 row produces 1.Map to gate: this is AND.Therefore, the assertion is correct. Verification / Alternative check: Boolean algebra: Y = A * B. De Morgan’s complement is NAND = (A * B)′, which flips the output for 11 only. This dual view reinforces the identification of AND from the verbal rule. Why Other Options Are Wrong: Incorrect: Conflicts with the canonical definition. Negative logic / Schmitt / delay: Logic polarity, hysteresis, or timing do not change the truth table of AND. Common Pitfalls: Confusing AND with OR (which is true for 11, 10, and 01). Remember: AND requires all inputs asserted; OR requires any input asserted. Final Answer: Correct

Question 17

NAND–AND relationship: Assess the claim: “The output of a NAND gate equals the inverted output of an AND gate.” Determine if this statement is accurate for standard positive logic.

Accepted Answer

Introduction / Context: NAND and AND are complementary operations. Many simplification techniques and universal-gate constructions rely on this exact relationship. Verifying the definition guards against common mistakes when reading mixed NAND/AND schematics or when replacing functions using universal NAND gates. Given Data / Assumptions: Positive logic, two inputs A and B. Standard Boolean semantics; no electrical edge cases considered. Concept / Approach: By definition, NAND(A,B) = NOT(AND(A,B)). In symbolic form: Y_NAND = (A * B)′. Therefore, if Y_AND = A * B, then Y_NAND = NOT(Y_AND). This matches the statement precisely and is true independent of implementation technology (TTL, CMOS, ECL). Step-by-Step Solution: Compute AND output: Y_AND = A * B.Invert it: Y = NOT(Y_AND).Recognize this equals NAND truth table (only 11 maps to 0, others to 1).Therefore, the claim is correct. Verification / Alternative check: Truth table confirms: AND: 00→0, 01→0, 10→0, 11→1. NAND is the complement: 00→1, 01→1, 10→1, 11→0, which is exactly the inversion of AND’s output row by row. Why Other Options Are Wrong: Incorrect or technology-limited options: Boolean identity does not depend on output topology or supply voltage; it is logically universal. Common Pitfalls: Mixing up NAND with NOR (the complement of OR). Remember: NAND complements AND; NOR complements OR. Final Answer: Correct

Logic Gates Questions