Question 1

Enable gating with a fixed-period clock A clock with period 1 µs is applied to an enable gate. If exactly six clock pulses must appear at the output, how long must the enable input remain active?

Accepted Answer

Introduction / Context: Enable gating is common in digital timing design, where a control line allows a subset of clock pulses to pass to counters or state machines. Understanding the relationship between clock period, desired pulse count, and enable width is foundational. Given Data / Assumptions: Clock period T = 1 µs. We need exactly N = 6 pulses at the output. Gate is ideal and passes pulses only while enable is active. Concept / Approach: The number of whole pulses that can pass equals the active time divided by the clock period. For an integer number of pulses with clean edges and no synchronization latency, the active time should be N * T. Step-by-Step Solution: Compute total time required: t_active = N * T.Substitute N = 6 and T = 1 µs.t_active = 6 * 1 µs = 6 µs.Therefore, enable must be asserted for 6 µs. Verification / Alternative check: Observe a timing diagram: with enable high across six consecutive rising edges, six pulses get through. If enabled for 3 µs, only three pulses pass; if for 12 µs, twelve pulses would pass. Why Other Options Are Wrong: 0 µs: no pulses can pass.3 µs: only 3 pulses at 1 µs period.12 µs: would pass 12 pulses, not 6. Common Pitfalls: Forgetting that the count depends on whole periods; edge alignment and gate propagation must be considered in real hardware to avoid off-by-one counts. Final Answer: Enable must be active for 6 µs.

Question 2

Boolean form of a NOR gate For a 2-input NOR logic gate with inputs A and B, which expression correctly represents its output?

Accepted Answer

Introduction / Context: NOR is a fundamental logic operator used as a universal gate. Recognizing its Boolean form enables algebraic manipulation, simplification, and design using only NOR devices. Given Data / Assumptions: Two inputs: A and B. Symbol conventions: + means OR, · means AND, and ' means NOT (complement). Concept / Approach: A NOR gate outputs the complement of the OR operation. Therefore, its output is the negation of A + B. This is directly written as Y = (A + B)' using the prime to denote inversion. Step-by-Step Solution: Start with OR: A + B is 1 when any input is 1.Apply inversion: NOR = NOT(OR) → Y = (A + B)'.Hence the output is 1 only when both A = 0 and B = 0. Verification / Alternative check: Truth table check: (0,0) → OR = 0 → NOT = 1; any other case has OR = 1 → NOT = 0, matching NOR behavior. Why Other Options Are Wrong: Y = A' + B': that is NOT A OR NOT B, not NOR.Y = (A · B)': complement of AND is NAND, not NOR.Y = A' · B': that is the DeMorgan form of NOR only after distributing the inversion, but without the outer parentheses it implies double inversion of each input, not the NOR operator as given. Common Pitfalls: Mixing DeMorgan equivalents: NOR equals A' · B' only if the bar is over A + B as a whole, then distributed; writing A' · B' directly can be misread. Final Answer: Y = (A + B)'

Question 3

TTL logic families comparison What functional difference distinguishes the 7400 and 7411 TTL integrated circuits?

Accepted Answer

Introduction / Context: Classic 74xx TTL parts are often identified by function numbers. Remembering core devices like 7400 and 7411 speeds up schematic reading and parts selection. Given Data / Assumptions: Series: 74xx TTL. Part 7400: standard building block. Part 7411: three-input gate device. Concept / Approach: The 7400 contains four independent 2-input NAND gates in one package. The 7411 contains three independent 3-input AND gates. This difference affects logic design density and required gate count. Step-by-Step Solution: Identify 7400: quad 2-input NAND.Identify 7411: triple 3-input AND.Choose the option that matches both facts. Verification / Alternative check: Standard pinout tables and TTL datasheets list these functions; many educational kits label them accordingly. Why Other Options Are Wrong: Options with four-input NANDs or ANDs do not match 7400/7411 datasheet specs.Options that swap AND/NAND are incorrect functions. Common Pitfalls: Confusing 7411 (3-input AND) with 7410 (3-input NAND). The final digit matters. Final Answer: 7400 has four two-input NAND gates; 7411 has three three-input AND gates

Question 4

Truth-table sizing How many distinct input combinations appear in the truth table of a six-input AND gate?

Accepted Answer

Introduction / Context: Truth tables enumerate all possible input states. Estimating their size is essential for exhaustive testing, simulation, and Karnaugh map construction. Given Data / Assumptions: Gate type: AND. Number of inputs: n = 6. Each input can be 0 or 1 (binary logic). Concept / Approach: For n binary inputs, the total number of unique input combinations is 2^n. This is independent of the specific logic function (AND, OR, etc.). Step-by-Step Solution: Compute 2^n with n = 6.2^6 = 64.Therefore, the truth table contains 64 rows (combinations). Verification / Alternative check: List smaller cases: 2 inputs → 4 rows; 3 inputs → 8 rows; 4 inputs → 16 rows. Pattern doubles with each additional input, confirming 6 → 64. Why Other Options Are Wrong: 32: corresponds to 5 inputs (2^5).48 and 128: do not equal 2^n for integer n = 6. Common Pitfalls: Confusing the number of combinations with the number of 1s in the output column; for an AND gate there is only one HIGH case (all inputs HIGH), but the table still lists all 64 input patterns. Final Answer: 64

Question 5

Inverter behavior Under what input condition does the output of a NOT (inverter) gate become logic HIGH?

Accepted Answer

Introduction / Context: The NOT gate (inverter) performs logical inversion, a cornerstone operation in digital systems. Understanding its truth behavior is essential for building more complex combinational and sequential circuits. Given Data / Assumptions: Ideal logic levels: LOW = 0, HIGH = 1. Properly powered and within specified input voltage ranges. Concept / Approach: An inverter outputs the complement of its input: Y = A'. Thus, when the input A is 0 (LOW), the output Y is 1 (HIGH), and vice versa. Step-by-Step Solution: Input A = 0 → Output Y = 1.Input A = 1 → Output Y = 0.Therefore, output is HIGH only when input is LOW. Verification / Alternative check: Examine the one-row truth table: A | Y → 0 | 1, 1 | 0. This matches the definition of inversion. Why Other Options Are Wrong: “Input is HIGH”: would produce a LOW at the output for an inverter.Power presence or absence does not define the logical state; without power the gate is nonfunctional, not logically HIGH. Common Pitfalls: Misinterpreting undefined or floating inputs; ensure inputs are tied to valid logic levels to avoid unpredictable outputs. Final Answer: the input is LOW

Question 6

Standard supply for TTL logic Transistor–transistor logic (TTL) devices are designed to operate from what nominal supply voltage?

Accepted Answer

Introduction / Context: Supply compatibility is crucial when mixing logic families. TTL has long served as a baseline for digital interfacing, with many systems designed around its nominal supply. Given Data / Assumptions: Logic family: TTL (e.g., 74xx standard TTL). We refer to classic, not low-voltage CMOS derivatives. Concept / Approach: Traditional TTL operates at a nominal VCC of 5 V, with defined noise margins and input thresholds around this level. Many modern interfaces still accommodate 5 V logic or provide level shifting for compatibility. Step-by-Step Solution: Identify family: TTL.Recall nominal supply: VCC ≈ 5 V.Therefore, the correct supply is 5-volt. Verification / Alternative check: Datasheets for 74LS, 74ALS, and standard 74 series specify VCC = 5 V ± tolerance. Why Other Options Are Wrong: 3 V: typical of some CMOS families (e.g., 3.3 V), not classic TTL.9 V and 12 V: used for analog subsystems or legacy logic families, not standard TTL. Common Pitfalls: Assuming all “74-series” are 5 V; 74HC/74HCT CMOS variants have wider ranges, and low-voltage families may run at 3.3 V—check the specific part. Final Answer: 5-volt supply

Question 7

Defining fan-out In digital logic specifications, fan-out is usually specified in terms of which quantity?

Accepted Answer

Introduction / Context: Fan-out indicates how many inputs a single logic output can reliably drive without violating voltage thresholds. It guides safe interconnections and prevents excessive loading. Given Data / Assumptions: Family-dependent input currents and thresholds. Fan-out abstracted as the number of “equivalent inputs” (unit loads). Concept / Approach: Manufacturers define one “unit load” as the input current that corresponds to a standard input of the same logic family. Fan-out equals the ratio of the driver’s guaranteed source/sink capability to one unit load, producing an integer count of inputs that can be driven. Step-by-Step Solution: Determine family input currents (e.g., TTL high/low input currents).Compute how many such inputs the driver can supply while meeting VOH/VOL specs.Express the result as a count of unit loads, which is the standard fan-out rating. Verification / Alternative check: Datasheets list fan-out as a number (e.g., “10 LS-TTL loads”), translating electrical limits into an easy design rule. Why Other Options Are Wrong: Voltage/current/wattage are underlying parameters, but the published fan-out is not directly stated as a voltage, current, or power value—it is a count of unit loads. Common Pitfalls: Driving mixed-family inputs without recalculating equivalent unit loads; CMOS inputs draw far less current, so the practical fan-out may be much higher. Final Answer: unit loads

Question 8

OR gate outcomes A 3-input OR gate has eight possible input combinations. For how many combinations will the output be logic HIGH?

Accepted Answer

Introduction / Context: Understanding OR gate behavior across all input states is foundational for designing combinational logic and estimating probabilities of output activity. Given Data / Assumptions: Inputs: 3 binary inputs → 2^3 = 8 combinations. OR function: output is 1 if any input is 1. Concept / Approach: The only case that yields a LOW output for an OR gate is when all inputs are LOW simultaneously. Every other combination produces a HIGH output. Step-by-Step Solution: Total combinations = 8.LOW output cases = exactly 1 (000).HIGH output cases = 8 − 1 = 7. Verification / Alternative check: Enumerate: 001, 010, 011, 100, 101, 110, 111 → all yield HIGH, confirming seven HIGH outputs. Why Other Options Are Wrong: 1 or 2: underestimate the number of HIGH cases.8: includes the all-zero case, which produces LOW for an OR. Common Pitfalls: Forgetting the all-zero case or confusing OR with NOR or AND behavior. Final Answer: 7

Question 9

NOR logic condition for HIGH output A multi-input NOR gate will produce a HIGH output under which input condition?

Accepted Answer

Introduction / Context: NOR gates are universal building blocks. Knowing precisely when their outputs go HIGH is vital for interpreting logic equations and designing control signals. Given Data / Assumptions: NOR = NOT(OR). Inputs are standard binary logic levels. Concept / Approach: Since OR outputs HIGH if any input is HIGH, its complement (NOR) outputs HIGH only in the single case where every input is LOW and the OR output would be LOW. Step-by-Step Solution: OR truth: any 1 among inputs → output 1.NOR truth: invert the OR result.Therefore, NOR outputs 1 only when inputs are all 0. Verification / Alternative check: Construct a two-row argument: OR(0,0,...,0) = 0 → NOR = 1; any other case OR = 1 → NOR = 0. Why Other Options Are Wrong: “All inputs HIGH” / “any input HIGH”: those make OR = 1 → NOR = 0.“Any input LOW”: includes mixed cases where other inputs may be HIGH; NOR would be LOW then. Common Pitfalls: Confusing NOR with NAND; NAND outputs LOW only when all inputs are HIGH, whereas NOR outputs HIGH only when all inputs are LOW. Final Answer: all inputs are LOW

Question 10

Digital logic control use-cases: The AND function can be used to ________, and the OR function can be used to ________. State the most generally correct statement for active-high and active-low control situations.

Accepted Answer

Introduction / Context: Logic gates are often used as “control elements.” A signal can be enabled (passed) or disabled (blocked) depending on a control input. Whether an AND gate or an OR gate performs the enabling or disabling depends on how the control signal is defined (active-high or active-low) and whether inputs are inverted. This question checks conceptual understanding rather than a single one-size-fits-all recipe. Given Data / Assumptions: The task is generic logic control (gating) rather than a specific family (TTL/CMOS). Control conventions may be active-high (logic 1 means “enable”) or active-low (logic 0 means “enable”). Inversions may be used around gates to realize either function. Concept / Approach: An AND gate passes a data signal when the control input is logic 1 (active-high enabling). An OR gate can also “enable” a path if the control provides a high that selects the desired path. Conversely, either gate can implement disabling/inhibit behavior with appropriate inversion (e.g., using a NOT on the control or using NAND/NOR). Therefore, both AND and OR are versatile: each can enable or disable depending on signal polarity and placement of inversion. Step-by-Step Solution: Active-high enable with AND: X = Data AND Enable.Active-low enable with OR: X = Data OR Enable_bar (with wiring such that Enable_bar = 0 passes Data).Inhibit with AND/OR: add inversion to the control or use NAND/NOR to block the path.Conclusion: Both gate types can be used for either enabling or disabling with the correct polarity. Verification / Alternative check: Examine truth tables for AND/OR with one input used as control; inserting NOT on either the control or the data swaps enable/inhibit roles. Why Other Options Are Wrong: enable, disable / disable, enable: too restrictive; not always true.detect, invert: detection is typically AND/OR; inversion is the NOT function, not AND/OR.amplify, rectify: analog terms, not logic-gate functions. Common Pitfalls: Assuming “AND = enable only” and “OR = disable only.” In practice, polarity and inversion determine behavior. Final Answer: enable or disable, enable or disable

Question 11

Standard TTL device identification: Which circuit number identifies the IC that contains four two-input AND gates (quad 2-input AND) in the 74xx TTL series?

Accepted Answer

Introduction / Context: Recognizing common 74xx TTL part numbers is a practical skill in digital electronics. The “quad two-input AND” device is used in countless designs for gating, decoding, and simple combinational logic. Given Data / Assumptions: We refer to classic 74xx TTL numbering. We seek the IC that implements four independent 2-input AND gates. Concept / Approach: Memorize or map the standard codes: 7408 = quad 2-input AND; 7432 = quad 2-input OR; 7404 = hex inverter; 7402 = quad 2-input NOR; 7411 = triple 3-input AND. Step-by-Step Solution: Check 7408 → known quad 2-input AND → matches.Cross-check others: 7404 (inverters), 7432 (OR), 7402 (NOR), 7411 (3-input AND).Therefore the answer is 7408. Verification / Alternative check: Any TTL pinout sheet or logic family table confirms these standard functions. Why Other Options Are Wrong: 7402: NOR, not AND.7404: inverters, not AND.7432: OR, not AND.7411: three 3-input ANDs, not four 2-input ANDs. Common Pitfalls: Confusing 7408 with 7411 (both AND devices but different input counts). Final Answer: 7408

Question 12

Troubleshooting with a logic probe and pulser: A probe on a gate’s output shows a dim (weak) indication. Toggling each input with a logic pulser does not change the output indication. What is the most likely fault?

Accepted Answer

Introduction / Context: Logic probes and pulsers are fast tools for diagnosing digital faults. A dim or indeterminate output that does not respond to input pulsing is a classic symptom used to infer an “open” or high-impedance condition where a node is floating rather than driven. Given Data / Assumptions: Output appears dim/weak on the probe. Using a pulser on each input does not change the output. Assume the device is not intentionally tri-stated and that VCC/GND are present. Concept / Approach: An open output (internal transistor failure, cracked solder joint, or broken trace) leaves the node floating. A high-impedance floating node can pick up stray charge and cause the probe to display a dim or ambiguous indication. If inputs are pulsed and still no deterministic transition is observed, the output is likely not being actively driven. Step-by-Step Solution: Observe: dim/ambiguous output.Test: pulse inputs → no output change.Inference: driver not asserting either high or low strongly → probable open output. Verification / Alternative check: Measure with a DMM for strong logic levels or use a scope; compare with another known-good gate pin on the same IC. Why Other Options Are Wrong: Supply low: would often affect many nodes and be confirmed by measuring VCC.Bad ground on probe: would cause erratic readings everywhere, not just one pin.Tristate: then enabling the output or driving control should change the state; also the scenario does not mention an OE pin.Clock too high: a pulser test is quasi-static; still should produce a response if the gate is functional. Common Pitfalls: Mistaking weak pull-ups/pull-downs for an open output; verify with resistance checks to VCC/GND. Final Answer: The output of the gate appears to be open.

Question 13

Boolean basics refresher: What is the correct Boolean expression for the output X of a three-input AND gate with inputs A, B, and C?

Accepted Answer

Introduction / Context: Understanding standard Boolean notation is essential for reading data sheets and designing logic. The AND function outputs logic 1 only when all inputs are 1. Given Data / Assumptions: Three inputs: A, B, C. Standard Boolean operators: “·” (AND), “+” (OR), and overbar/apostrophe for NOT. Concept / Approach: The n-input AND gate is expressed as a product of the inputs. Therefore, a three-input AND is X = A · B · C. Step-by-Step Solution: Identify gate → AND.Use product form → multiply all inputs.Result → X = A · B · C. Verification / Alternative check: Truth table shows X = 1 only for A = B = C = 1, matching the product term behavior. Why Other Options Are Wrong: A + B + C: OR function, not AND.A – B – C and A $ B $ C: nonstandard/incorrect operators.X = A(B + C): mixed expression that does not require all three inputs to be 1. Common Pitfalls: Confusing sum (OR) with product (AND) notation. Final Answer: X = A · B · C

Question 14

Write the inverter relationship: For a NOT (inverter) logic gate with input C and output Y, which Boolean expression correctly represents the function?

Accepted Answer

Introduction / Context: An inverter (NOT gate) outputs the logical complement of its input. Fluency with equivalent notations is essential: apostrophe ('), overbar, and the keyword NOT all mean logical negation. Given Data / Assumptions: Single input C and single output Y. Standard Boolean shorthand is allowed (apostrophe to denote complement). Concept / Approach: If the input is 1, the output must be 0, and vice versa. The concise expression is Y = C' (read as “Y equals C complement”). Textbooks may also write Y = NOT C or place a bar over C. Step-by-Step Solution: Identify function: inverter.Apply complement: Y equals the logical NOT of C.Choose compact notation: Y = C'. Verification / Alternative check: Truth table confirms that when C = 0 → Y = 1, and when C = 1 → Y = 0, exactly matching a complement. Why Other Options Are Wrong: Y = C: that is a buffer, not an inverter.Y = NOT C: conceptually correct, but the question expects a compact Boolean expression; we accept apostrophe form.Y = C XOR 1: equals C' only if XOR is interpreted as inversion, but XOR with 1 in Boolean algebra does invert; however, that is not standard notation for expressing a NOT gate block symbolically.Y = C + C: simplifies to C, not an inversion. Common Pitfalls: Confusing complement notation and using ambiguous arithmetic symbols instead of Boolean notation. Final Answer: Y = C'

Question 15

IC packaging terminology: When used with an integrated circuit part description, the term “QUAD” indicates the device contains how many identical circuits (functions) in one package?

Accepted Answer

Introduction / Context: Digital logic ICs are commonly described as single, dual, triple, quad, or hex, indicating how many identical gate functions are integrated in one package. This helps with part selection and schematic reading. Given Data / Assumptions: “Quad” is a standard descriptor across TTL/CMOS families. Examples: 7408 (quad 2-input AND), 7432 (quad 2-input OR). Concept / Approach: “Quad” means four. Therefore a quad IC contains four identical functions (e.g., four AND gates) within the package. Step-by-Step Solution: Interpret term “quad.”Map to quantity → 4.Answer: 4 circuits per package. Verification / Alternative check: Compare with “hex” (6 inverters in 7404) and “dual” op-amps (two amplifiers per chip). Why Other Options Are Wrong: 2, 6, 8, 12 circuits: do not match the definition of “quad.” Common Pitfalls: Confusing “quad” with “hex” (common because 7404 is hex inverters, not quad). Final Answer: 4 circuits

Question 16

Truth-table reasoning: For a 3-input AND gate, there are 8 possible input combinations. How many of those combinations will produce a HIGH output?

Accepted Answer

Introduction / Context: AND gates output HIGH only when all inputs are HIGH. Counting how many input combinations yield a HIGH output reinforces intuition about multi-input logic behavior and probabilities in random logic testing. Given Data / Assumptions: Three inputs → 2^3 = 8 combinations. AND function requires all inputs to be 1 for a 1 output. Concept / Approach: Enumerate conceptually: only the combination A = 1, B = 1, C = 1 satisfies the AND condition. Every other combination contains at least one 0 and therefore forces the output to 0. Step-by-Step Solution: Total combos = 2^3 = 8.High output cases for AND = number of “all ones” cases = 1.Thus, answer = 1. Verification / Alternative check: Create a quick truth table and verify only the last row (1,1,1) yields HIGH. Why Other Options Are Wrong: 2 or 4: would require additional satisfying combinations which do not exist for AND.7 or 8: these are typical for OR/NOR/always-on behaviors, not AND. Common Pitfalls: Confusing AND with OR, where many more combinations produce HIGH. Final Answer: 1

Question 17

Four-input OR expression: Select the correct Boolean expression for a 4-input OR gate with inputs A, B, C, and D and output Y.

Accepted Answer

Introduction / Context: Recognizing canonical Boolean forms is indispensable for design and verification. The OR function outputs HIGH if any input is HIGH. Given Data / Assumptions: Inputs: A, B, C, D. Operator “+” denotes OR; “·” denotes AND. Concept / Approach: A 4-input OR gate is written as the sum of all inputs: Y = A + B + C + D. Step-by-Step Solution: Map function → OR.Write as sum of literals → A + B + C + D.Thus Y = A + B + C + D. Verification / Alternative check: Truth table shows output HIGH for any case with at least one input HIGH, matching the sum form. Why Other Options Are Wrong: A·B·C·D: AND of all four inputs, not OR.Minus sign and dollar sign are not standard Boolean OR operators.(A + B)(C + D): equals AC + AD + BC + BD, which is not a simple 4-input OR. Common Pitfalls: Mixing arithmetic and Boolean operators or expanding incorrectly. Final Answer: Y = A + B + C + D

Question 18

Three-input OR expression: Choose the correct Boolean expression for a 3-input OR gate with inputs A, B, C and output X.

Accepted Answer

Introduction / Context: Boolean notation links directly to gate symbols and truth tables. The OR operator is denoted by a plus sign and produces a HIGH output if any input is HIGH. Given Data / Assumptions: Inputs: A, B, C. Standard operators: “+” for OR, “·” for AND. Concept / Approach: A 3-input OR gate is written as the sum of the three input literals: X = A + B + C. Step-by-Step Solution: Identify the intended function → OR across three signals.Write directly → X = A + B + C. Verification / Alternative check: Construct a truth table and verify that whenever any input is 1, X is 1; only A = B = C = 0 yields 0. Why Other Options Are Wrong: X = A + B: ignores C.X = ABC: AND of three inputs.X = A + BC or (A + B)C: mixed expressions not equivalent to a plain 3-input OR. Common Pitfalls: Confusing OR with mixed sum-of-products structures. Final Answer: X = A + B + C

Question 19

Digital logic — 3-input AND gate behavior For an AND gate with three inputs A, B, and C, identify the exact input condition under which the output is HIGH (logic 1).

Accepted Answer

Introduction / Context: This question checks fundamental understanding of the AND operation in digital electronics. AND gates are ubiquitous in control logic, enable lines, and safety interlocks, where a HIGH output should occur only when all required conditions are simultaneously true. Given Data / Assumptions: A standard 3-input AND gate with inputs A, B, and C. Logic levels: 0 represents LOW, 1 represents HIGH. No inversion bubbles are present on inputs or output. Concept / Approach: The Boolean equation for a 3-input AND gate is X = A * B * C (often written X = ABC). The product of binary variables equals 1 only if every factor equals 1. If any input is 0, the product becomes 0 immediately, forcing a LOW output. Step-by-Step Solution: Let X = A * B * C.Check case A = 1, B = 1, C = 1: X = 1 * 1 * 1 = 1.If any one input is 0 (e.g., A = 1, B = 1, C = 0), then X = 1 * 1 * 0 = 0.Therefore, only the all-ones input produces a HIGH output. Verification / Alternative check: Construct the 3-input AND truth table. Out of the 8 possible input triplets, exactly one row (1,1,1) yields X = 1; the other seven rows contain at least one zero and yield X = 0. This matches the product rule of Boolean algebra. Why Other Options Are Wrong: A = 1, B = 1, C = 0 → X = 0 because one input is LOW. A = 0, B = 0, C = 0 → X = 0 since all are LOW. A = 1, B = 0, C = 1 → X = 0 because B is LOW. Common Pitfalls: Confusing AND with OR. OR would output HIGH if any input is HIGH; AND requires all inputs HIGH. Assuming two HIGHs are “enough”—for AND, every input must be HIGH without exception. Final Answer: A = 1, B = 1, C = 1

Question 20

Gate equivalence in digital design A NOR logic gate performs the same overall function as which gate when an inverter is connected to that gate’s output?

Accepted Answer

Introduction / Context: Gate equivalence is essential when substituting parts or simplifying designs. Recognizing how composite gate configurations replicate standard functions like NOR helps with logic minimization and hardware implementation choices. Given Data / Assumptions: NOR is defined as logical NOT of OR. Boolean “+” denotes OR; NOT indicates inversion (complement). We compare NOR to a single basic gate followed by an inverter. Concept / Approach: The NOR function is X = NOT(A + B) for two inputs (and extends similarly for more inputs). That is exactly what occurs if an OR gate’s output is fed into an inverter. Hence, an OR followed by NOT is equivalent to a single NOR gate symbol. Step-by-Step Solution: Start with OR: Y = A + B.Invert the result: X = NOT(Y) = NOT(A + B).By definition, X equals the NOR of A and B. Verification / Alternative check: Compare truth tables. For inputs 00, 01, 10, 11, the OR-then-invert sequence gives outputs 1, 0, 0, 0, which is the NOR truth table exactly. Why Other Options Are Wrong: AND then NOT gives NAND, not NOR. NAND is NOT(AND); NOR is NOT(OR). They are distinct universal gates. “none of the above” is incorrect because OR followed by an inverter is correct. Common Pitfalls: Confusing De Morgan companions: NAND vs. NOR. Mixing arithmetic “+” with Boolean “+”; Boolean “+” represents logical OR. Final Answer: OR

Logic Gates Questions