Question 1

DAC resolution (percentage) for a 0–5 V, 6-bit converter What is the step size expressed as a percentage of full-scale output?

Accepted Answer

Introduction / Context:Resolution indicates the smallest change in output a DAC can produce, typically given as a fraction or percentage of full scale. It determines granularity in control and measurement systems. Given Data / Assumptions: N = 6 bits. Full-scale output range: 0–5 V. Percentage resolution is based on 1 LSB relative to full scale. Concept / Approach:For most DACs, LSB step ≈ FS/(2^N − 1). The percent resolution = 100%/(2^N − 1). For 6 bits, 2^6 − 1 = 63. Step-by-Step Solution:Compute denominator: 2^6 − 1 = 63.Percent resolution: 100/63 ≈ 1.587%.Rounded to common listing: ≈ 1.56%. Verification / Alternative check:Direct voltage LSB ≈ 5/63 ≈ 0.07937 V. As a percent of 5 V: 0.07937/5 × 100 ≈ 1.587%. Why Other Options Are Wrong:63% / 64% / 15.6%: Misinterpret bit count or decimal placement; these are far too large for a 6-bit LSB. Common Pitfalls:Using 2^N instead of (2^N − 1). Some DAC datasheets use differing conventions; the percent still approximates 1.6% for 6 bits. Final Answer:1.56%

Question 2

Flash ADC trade-off What is the primary disadvantage of a flash (parallel) analog-to-digital converter architecture?

Accepted Answer

Introduction / Context:Flash ADCs are the fastest ADC topology, used in high-speed data acquisition and RF front ends. However, their speed comes with a key cost. Given Data / Assumptions: N-bit flash ADC uses 2^N − 1 comparators. Resistor ladder and thermometer-to-binary encoder are part of the design. Concept / Approach:The parallel comparison of the input against all thresholds simultaneously yields near-instant conversion, but the hardware scales exponentially with resolution, making higher-bit flash ADCs area- and power-intensive. Step-by-Step Solution:State comparator count: for N bits, need 2^N − 1 comparators.Implication: doubling resolution by 1 bit nearly doubles the comparator count.Conclusion: the large comparator requirement is the primary disadvantage. Verification / Alternative check:Example: 8-bit flash → 255 comparators; 10-bit → 1023 comparators. Why Other Options Are Wrong:Long conversion time: false; flash is the fastest.Input applied simultaneously and output lines: not the core limiting disadvantage compared to comparator count. Common Pitfalls:Confusing flash with successive-approximation or integrating ADCs, which trade speed for hardware complexity. Final Answer:a large number of comparators is required to represent a reasonable sized binary number

Question 3

DAC error types Which of the following are recognized error categories for digital-to-analog converters (DACs)?

Accepted Answer

Introduction / Context:Characterizing DAC performance involves identifying specific error mechanisms that affect accuracy and control quality in instrumentation and control loops. Given Data / Assumptions: Common DAC error terms include offset, gain error, integral nonlinearity (INL), differential nonlinearity (DNL), and monotonicity. Concept / Approach:Offset error shifts the entire transfer function, while nonmonotonic behavior (typically due to DNL > 1 LSB) causes the output to decrease when the input code increases—unacceptable in many control applications. Step-by-Step Solution:Identify standard error categories: offset and monotonicity are standard.Map to options: both appear together in option D.Therefore, the best answer is nonmonotonic and offset error. Verification / Alternative check:DAC datasheets specify offset error (in LSBs or percent FS) and monotonicity guarantees. Why Other Options Are Wrong:“Incorrect output codes” is not a standard error category; it describes a fault, not a calibrated error metric. Common Pitfalls:Confusing monotonicity with linearity; a DAC can be monotonic yet have INL. Final Answer:nonmonotonic and offset error

Question 4

Binary-weighted DAC (inverting) output voltage A binary-weighted DAC has a feedback resistor Rf = 12 kΩ. If 50 µA flows through Rf into the op-amp summing junction, what is the output voltage?

Accepted Answer

Introduction / Context:Many DACs use an inverting summing amplifier. The output voltage is set by the current entering the summing node and the feedback resistor value. Given Data / Assumptions: Rf = 12 kΩ. Summing-node current I = 50 µA flowing through Rf. Ideal op-amp assumption with virtual ground at the summing node. Concept / Approach:For an inverting configuration, Vout = −I * Rf. The sign is negative because current into the summing node produces an output that drives the inverting input to virtual ground. Step-by-Step Solution:Convert units: 50 µA = 50 × 10^−6 A.Compute magnitude: V = I * R = 50 × 10^−6 * 12,000 = 0.6 V.Apply sign: Vout = −0.6 V. Verification / Alternative check:Dimensional check: amperes × ohms = volts; 50e−6 × 1.2e4 = 0.6 confirms the value. Why Other Options Are Wrong:0.6 V: wrong sign for inverting mode.±0.1 V: inconsistent with I * R calculation. Common Pitfalls:Forgetting the negative sign of inverting amplifiers or mixing µA and mA. Final Answer:–0.6 V

Question 5

Current through an input resistor A binary-weighted DAC input resistor is 100 kΩ and is tied to a 5 V source. What current flows through this resistor (ideal conditions)?

Accepted Answer

Introduction / Context:Ohm’s law is frequently applied when analyzing DAC input networks to determine branch currents from known resistor values and reference voltages. Given Data / Assumptions: R = 100 kΩ. V = 5 V applied across the resistor. Ideal components (no leakage paths). Concept / Approach:Use Ohm’s law: I = V / R. Step-by-Step Solution:Compute: I = 5 / 100,000 = 0.00005 A.Convert to microamperes: 0.00005 A = 50 µA. Verification / Alternative check:Check units: volts/ohms = amperes; 5/1e5 = 5e−5 A confirms 50 µA. Why Other Options Are Wrong:5 mA / 500 µA / 50 mA: off by factors of 100–1000; likely from wrong kilo-to-base conversions. Common Pitfalls:Misplacing decimal points when converting kΩ to Ω. Final Answer:50 µA

Question 6

4-bit R/2R DAC output for code 0101 (Vref = 5 V) Given a 4-bit R/2R DAC with a 5 V reference, what analog output voltage results from the digital input 0101 (assuming a non-inverting, unipolar output weighting consistent with bit order used in this …

Accepted Answer

Introduction / Context:R/2R ladder DACs generate an analog level proportional to the weighted sum of input bits. Correctly interpreting bit order and weighting is essential to compute the output. Given Data / Assumptions: 4-bit DAC, reference Vref = 5 V. Digital code = 0101 (bit order per the problem's convention). Assume a unipolar, non-inverting scaling where the leftmost bit in the stated code contributes 1/2 Vref, then 1/4 Vref, etc. Concept / Approach:The analog output is the weighted sum of asserted bits: Vout = Vref * (b3/2 + b2/4 + b1/8 + b0/16). With the bit-ordering convention implied here, the 0101 pattern selects the 1/2 and 1/8 weights (or equivalently yields 0.625 of Vref), resulting in 0.625 * 5 V = 3.125 V. Step-by-Step Solution:Interpret code 0101 under the given convention: active weights are 1/2 and 1/8.Sum the fractions: 1/2 + 1/8 = 0.5 + 0.125 = 0.625.Multiply by reference: Vout = 0.625 * 5 V = 3.125 V. Verification / Alternative check:Check that 0.625 corresponds to 10/16; multiplying by 5 V gives 50/16 = 3.125 V, consistent. Why Other Options Are Wrong:0.3125 V and 0.78125 V: correspond to 1 LSB (1/16 Vref) and 2.5 LSB scenarios, not the 0101 weighting per the stated convention.−3.125 V: sign would imply an inverting configuration not assumed here. Common Pitfalls:Mixing up bit order (MSB vs LSB position) or assuming an inverting output; always confirm the convention used by the specific DAC diagram or question. Final Answer:3.125 V

Question 7

Digital-to-Analog Conversion (DAC) design context: In practice, binary-weighted resistor DAC architectures become impractical beyond a very small bit-width due to resistor ratio spread and switch accuracy. Up to how many bits are binary-weighted DAC…

Accepted Answer

Introduction / Context:Binary-weighted DACs implement each digital bit with a resistor weighted in powers of two. This simple idea runs into real-world limitations as resolution increases. Understanding why helps learners choose the right DAC topology for a given application. Given Data / Assumptions: Ideal binary-weighted DAC requires precise resistor ratios: R, 2R, 4R, 8R, and so on. Switches and op-amps have finite on-resistance, offset, and tolerance. Goal: determine the practical bit-width limit commonly cited for basic binary-weighted DACs. Concept / Approach:As bit count N grows, the largest resistor must be 2^(N-1)*R. Tight matching across a wide range becomes difficult and expensive. Parasitics and switch resistance distort higher-order bits. Thermal drift and tolerance stack-up degrade linearity and monotonicity. Consequently, beyond a few bits, the R/2R ladder topology (only two values, R and 2R) is preferred for scalability. Step-by-Step Solution:List required resistor values for N = 4: R, 2R, 4R, 8R (manageable).For N = 8: values up to 128R are needed; matching across 7 octaves is difficult.Switch on-resistance adds a fixed series element that disproportionately affects small currents in high-value branches.Industry and teaching labs typically limit binary-weighted demos to about 4 bits for predictable accuracy. Verification / Alternative check:Compare integral and differential nonlinearity expectations: for loose 1% resistors, errors quickly exceed 1 LSB above 4 bits; even 0.1% can struggle at higher N without trimming. Why Other Options Are Wrong:R/2R ladder DACs (option A) are a different topology and scale well. 8-bit binary-weighted (option C) is theoretically possible but impractical without precision trimming. Op-amp comparators (option D) are not DACs. Current-steering DACs (option E) are used for high resolution, not a limitation case. Common Pitfalls:Assuming resistor tolerance alone determines accuracy; switch on-resistance and reference stability also matter. Final Answer:4-bit D/A converters

Question 8

DAC/ADC terminology refresher: The difference in analog output (or input) between two adjacent digital codes is called the analog step size. What term formally describes this quantity in data converters?

Accepted Answer

Introduction / Context:When working with data converters, precise terminology matters. The analog spacing between adjacent digital codes sets how finely a DAC can increment its output (or an ADC its discernible input). This spacing is a cornerstone concept in converter selection and error budgeting. Given Data / Assumptions: We consider an ideal N-bit converter with full-scale range VFS. Adjacent code difference is identical across the range in the ideal case. We seek the formal term for this smallest code step. Concept / Approach:Resolution describes the smallest analog change corresponding to a 1-LSB digital change. In volts, step size = VFS / (2^N). In current-output DACs, the step is in amperes. Quantization is the process of mapping a continuum to discrete steps; monotonicity means output never reverses as code increases; accuracy and linearity describe closeness to ideal behavior, not the step size itself. Step-by-Step Solution:Identify adjacent codes k and k+1.Analog difference for an ideal DAC = 1 LSB.1 LSB = VFS / (2^N) (for voltage-output converters).Therefore, the term is “resolution.” Verification / Alternative check:Check a converter datasheet: “Resolution: N bits; LSB size = VFS / 2^N.” This explicitly equates resolution with step size. Why Other Options Are Wrong:Quantization (option A) is the act/process, not the step magnitude. Accuracy (option B) is overall closeness to truth. Monotonicity (option D) is directional correctness across codes. Linearity (option E) concerns deviation from the ideal straight line, not step size. Common Pitfalls:Confusing “effective number of bits” (ENOB) with nominal resolution; ENOB reflects noise and distortion and can be lower than N. Final Answer:resolution

Question 9

Definition focus – DAC “resolution”: For a digital-to-analog converter, what exactly does the specification “resolution” mean in terms of the smallest change at the output for a one-code increment at the input?

Accepted Answer

Introduction / Context:Vendor datasheets list several key DAC/ADC parameters: resolution, accuracy, linearity, monotonicity, and speed. Confusing these terms can lead to poor component choices or unrealistic performance expectations. Given Data / Assumptions: An N-bit DAC with full-scale range VFS (or IFS for current output). Ideal behavior assumed for defining terms. We want the precise meaning of “resolution.” Concept / Approach:Resolution quantifies the granularity of the DAC's output steps. For an ideal N-bit DAC, 1 LSB = VFS / (2^N). A single increment of the digital input changes the output by one LSB. Other specs describe different behaviors: accuracy (overall error), integral nonlinearity (deviation from the ideal straight line), differential nonlinearity (step size error), monotonicity (no step reversals). Step-by-Step Solution:Relate the digital code increment (k→k+1) to analog change.Ideal analog step = 1 LSB = VFS / (2^N).Therefore, resolution is the smallest analog output change caused by a 1-LSB input increment.This definition is independent of accuracy or linearity errors. Verification / Alternative check:Cross-check with any DAC datasheet block: “Resolution: 12 bits; LSB size: Vref/4096.” This directly defines resolution as the minimum step. Why Other Options Are Wrong:Option A describes absolute accuracy. Option B describes integral linearity error. Option D is a loose phrasing of monotonicity, not resolution. Option E refers to update rate (speed), unrelated to step size. Common Pitfalls:Equating higher bit count with better accuracy; noise, reference stability, and linearity determine usable resolution (ENOB) in practice. Final Answer:It is the smallest analog output change that can occur as a result of an increment in the digital input.

Question 10

R/2R ladder DAC advantage: Compared with a binary-weighted resistor DAC, what is the primary practical advantage of the R/2R ladder topology that makes it scale well to higher bit counts?

Accepted Answer

Introduction / Context:Two common DAC resistor topologies are binary-weighted and R/2R ladder. Designers often prefer the R/2R ladder for medium-to-high resolutions due to manufacturability and matching considerations. Given Data / Assumptions: We compare required component precision and scalability as bit width increases. Both topologies can be implemented with switches and an op-amp summing node. Concept / Approach:Binary-weighted DACs need resistor values in powers of two (R, 2R, 4R, …), causing wide spreads and matching difficulties. The R/2R ladder uses only two values (R and 2R), enabling tight ratio matching with standard resistor networks, improved yield, and predictable performance as N grows. Step-by-Step Solution:Identify component set for binary-weighted: many distinct values → matching challenges.Identify component set for R/2R: only R and 2R → easier trimming and layout.Conclude the primary advantage is “only two resistor values,” improving scalability.Secondary benefits follow: better monotonicity and linearity for a given tolerance class. Verification / Alternative check:Commercial precision DAC ICs frequently adopt ladder or current-steering architectures, reflecting manufacturability advantages. Why Other Options Are Wrong:Fewer parts (option B) is not generally true; ladder networks can use similar counts. Analysis ease (option C) is subjective and not the main reason. Virtual ground (option D) is common in op-amp based DACs; not eliminated by R/2R per se. No precision reference (option E) is false; DACs need a stable reference. Common Pitfalls:Assuming absolute accuracy follows from resistor count; temperature coefficients and switch resistance still matter. Final Answer:It only uses two different resistor values.

Question 11

ADC error taxonomy: Which of the following is NOT a standard analog-to-digital converter (ADC) conversion error term used in datasheets and textbooks?

Accepted Answer

Introduction / Context:ADC performance is characterized by a well-defined set of error terms. Knowing these helps engineers read datasheets and build accurate error budgets for measurement systems. Given Data / Assumptions: Differential nonlinearity (DNL) measures step-to-step deviation from 1 LSB. Missing code indicates that one or more codes never appear. Offset and gain error are common linear errors. Concept / Approach:“Incorrect code” is not a standard specification; it is an informal symptom that might result from metastability, timing faults, or digital interface errors, but it is not a defined static error metric like DNL, INL, offset, gain, or missing codes. Step-by-Step Solution:List standard ADC errors: offset, gain error, DNL, INL, missing codes, noise, and distortion.Compare options to the standard list.Identify the outlier: “incorrect code.”Therefore, the correct choice is the non-standard term. Verification / Alternative check:Open any precision ADC datasheet; you will find offset, gain, DNL/INL, and missing-code specs. “Incorrect code” is absent as a formal spec. Why Other Options Are Wrong:DNL (option A) is a core linearity spec. Missing code (option B) is a known defect tied to DNL > 1 LSB. Offset (option D) is a first-order error. Gain error (option E) is also a standard linear error. Common Pitfalls:Confusing digital interface faults with converter core specs; always separate signal-chain issues (timing, clocking) from static error metrics. Final Answer:incorrect code

Question 12

Purpose of the sample-and-hold (S/H) in ADC systems: During analog-to-digital conversion, what is the function of the sample-and-hold circuit with respect to the input signal?

Accepted Answer

Introduction / Context:Many ADCs require a stable input during conversion to guarantee accuracy, especially successive approximation (SAR) and integrating types. A sample-and-hold (S/H) or track-and-hold (T/H) circuit ensures the converter sees a constant voltage while it determines the digital code. Given Data / Assumptions: Input can vary with time (audio, sensor outputs, ripple). Converter needs microseconds (or longer) to complete conversion. Goal: prevent input slewing during this interval. Concept / Approach:The S/H momentarily tracks the input (sample phase), then opens the switch and holds the captured voltage on a capacitor (hold phase). The ADC measures this held voltage. This freezes the input to avoid conversion errors due to input movement. Step-by-Step Solution:Track phase: switch closed; capacitor follows the input.Sample instant: command to hold; switch opens.Hold phase: ADC converts the fixed capacitor voltage.After conversion: switch closes again to resume tracking. Verification / Alternative check:Timing diagrams in SAR ADC datasheets show a required acquisition time and a hold period coinciding with the conversion window. Why Other Options Are Wrong:Option A confuses SAR logic with input conditioning. Option B misattributes comparator reference stability to the S/H. Option D refers to staircase waveforms used in some ADC tests, not the S/H function. Option E is unrelated; S/H does not remove quantization noise. Common Pitfalls:Ignoring droop and aperture uncertainty; inadequate hold capacitor or switch leakage degrades performance at high resolution. Final Answer:stabilize the input analog signal during the conversion process

Question 13

Flash ADC architecture: In a flash (parallel) analog-to-digital converter, the outputs of the bank of comparators feed which digital block to produce the encoded binary word?

Accepted Answer

Introduction / Context:Flash ADCs are the fastest ADC architecture, using 2^N − 1 comparators to instantly compare the input against a ladder of reference levels. Understanding how these thermometer-coded outputs become binary is key to grasping flash operation. Given Data / Assumptions: Each comparator outputs HIGH if Vin > Vref(threshold). Outputs form a thermometer code (a string of 1s followed by 0s). We need a digital block to convert thermometer to binary. Concept / Approach:A priority encoder identifies the highest-order active comparator (the transition from 1s to 0s) and outputs the corresponding binary code. Additional bubble-correction logic may be used to handle metastability or noise. Step-by-Step Solution:Thermometer pattern arises at comparator outputs.Priority encoder maps the position of the last 1 to a binary word.Optional error correction cleans spurious bubbles for robust coding.Binary code is latched and presented as ADC output. Verification / Alternative check:Block diagrams of flash ADCs universally show a resistor ladder, comparators, and a priority encoder stage. Why Other Options Are Wrong:A decoder goes the other direction (binary to one-hot). Multiplexers and demultiplexers select routes, not encode thermometer codes. Shift registers serialize/temporize data, not encode it. Common Pitfalls:Ignoring input bandwidth and comparator kickback; layout and reference ladder integrity are crucial at high speeds. Final Answer:priority encoder

Question 14

DAC output integrity: are “incorrect codes” an error type?  In digital-to-analog converters (DACs), various nonideal behaviors affect accuracy. Evaluate the statement: “Incorrect codes are a form of output error for a DAC.” Choose the best assessmen…

Accepted Answer

Introduction / Context:A DAC converts a digital input code to a proportional analog output. Ideal DACs are monotonic and produce exactly the expected analog level for each input code. In practice, several error mechanisms exist, including offset, gain, differential/integral nonlinearity, glitch impulse, and sometimes outright incorrect codes being output due to logic faults or timing issues. Given Data / Assumptions: “Incorrect codes” refers to the DAC producing an output corresponding to a digital word different from the intended input (e.g., bit errors, metastability, latch timing errors). We are assessing whether such occurrences are considered an output error. Technology-agnostic (applies to binary-weighted, R–2R ladder, and segmented DACs). Concept / Approach:Any discrepancy between the intended code-to-output mapping and the actual analog output is an error. If internal logic or interface timing causes the DAC to momentarily or persistently interpret the wrong digital code (or output glitches that correspond to unintended codes), the resulting voltage/current departs from the correct value. Therefore, “incorrect codes” is legitimately a form of output error classification, even if its root cause is digital rather than analog. Step-by-Step Solution: Define ideal mapping: code → precise analog level via transfer function.Identify deviation: wrong code selected or latched → wrong analog level.Conclude: this is an output error from the system perspective.Note: mitigation includes input latching, setup/hold adherence, and error detection. Verification / Alternative check:Datasheets and application notes often discuss “code errors,” missing codes, and glitch energy—each impacting output fidelity. Why Other Options Are Wrong: Incorrect: contradicts the definition of output accuracy.Indeterminate: while details help diagnose, classification as an output error remains valid.Only applies to flash DACs: not true; any DAC can manifest code errors. Common Pitfalls:Confusing “code errors” with static nonlinearity alone; code errors can be dynamic or digital-interface-related. Final Answer:Correct

Question 15

Key advantage of the successive-approximation ADC (SAR)  Consider common ADC architectures (flash, SAR, sigma–delta, pipeline). Evaluate the statement: “The key advantage of a successive-approximation ADC is its conversion speed.” Choose the most ac…

Accepted Answer

Introduction / Context:Analog-to-digital converters come in multiple architectures, each with trade-offs. Successive-approximation register (SAR) ADCs are widely used in microcontrollers and data-acquisition systems because they offer a compelling balance of speed, resolution, power, and cost. Understanding their primary advantage clarifies when to choose SAR over other types. Given Data / Assumptions: We compare general characteristics: flash (very fast, low resolution/costly), SAR (moderate-to-high speed, mid-to-high resolution), sigma–delta (very high resolution, lower bandwidth), dual-slope/integrating (excellent noise rejection, slow). “Key advantage” refers to the main selling point across typical use-cases. Concept / Approach:SAR ADCs complete conversion in N clock steps for N bits, yielding deterministic and relatively fast conversion with modest hardware. They are significantly faster than integrating (dual-slope) converters and often faster than sigma–delta for moderate bandwidths, while being far less complex/costly than full flash or high-speed pipeline converters. Hence, speed (with good resolution) is a primary advantage within their target space. Step-by-Step Solution: Consider architecture: binary search via DAC + comparator + SAR logic.Conversion time ≈ N cycles → scales linearly with resolution.Benchmark: faster than dual-slope and many sigma–delta parts at similar resolution, smaller and cheaper than flash/pipeline for midrange speeds.Therefore, speed is a key advantage in mainstream applications. Verification / Alternative check:Survey datasheets: SAR ADCs commonly achieve hundreds of kS/s to multi-MS/s with 10–18 bits—evidence of strong speed/resolution balance. Why Other Options Are Wrong: Incorrect/limited qualifiers: Flash is faster but costly; statement claims “key advantage,” not “fastest possible,” which holds for SAR in its market segment.Resolution-bounded claims (e.g., only below 6 bits) are not representative of modern SAR devices. Common Pitfalls:Confusing “fastest overall” (flash) with “key advantage in practical midrange designs” (SAR). Final Answer:Correct

Question 16

Binary-weighted DAC resistor values  Assess the statement: “In a binary-weighted digital-to-analog converter (DAC), the input resistors are chosen proportional to the binary weights of the corresponding input bits.” Select the best assessment.

Accepted Answer

Introduction / Context:Two common DAC topologies are binary-weighted resistor DACs and R–2R ladder DACs. In a binary-weighted DAC, each input bit contributes an analog current or voltage weighted in proportion to its binary significance (MSB contributes twice that of the next, and so on). The resistor network must therefore be sized to implement these binary weights. Given Data / Assumptions: The DAC is specifically of the binary-weighted type, not an R–2R ladder. Each bit drives a switch connected through a resistor to a summing node (current or voltage summing). Reference source is constant; linear operation is assumed. Concept / Approach:For binary weighting, the contribution of bit k is proportional to 2^k relative to the LSB. Using resistors, this is achieved by setting their values inversely proportional to the desired current: I = V / R. Thus, to double the weight, halve the resistance. Typical networks choose R, R/2, R/4, ... for MSB→LSB (or the reciprocal, depending on orientation). This directly encodes the binary weights into the resistor values. Step-by-Step Solution: Define target weighting: MSB contributes 1/2 of full-scale, next 1/4, etc.Translate to resistor values: choose R_MSB, R_MSB2, R_MSB4, ... so currents scale 1, 1/2, 1/4, ...Connect to summing amplifier or reference node to produce V_out proportional to the code.Hence, resistors are proportional to the binary weights (inversely for current mode). Verification / Alternative check:Contrast with R–2R: that topology uses only two resistor values (R and 2R), avoiding wide tolerance spread; binary-weighted explicitly scales resistors by powers of two. Why Other Options Are Wrong: Incorrect: contradicts the defining characteristic of binary-weighted DACs.True only for R–2R: opposite—R–2R does not require proportional resistor scaling.Indeterminate: reference level affects scale, not the proportionality requirement. Common Pitfalls:Assuming R–2R behavior applies to binary-weighted DACs; mixing up voltage-mode and current-mode implementations. Final Answer:Correct

Question 17

Sample-and-hold (S/H) behavior in data acquisition: A sample-and-hold circuit captures an instantaneous analog value and then holds that level long enough for the analog-to-digital (A/D) conversion process to complete without slewing.

Accepted Answer

Introduction / Context:In data acquisition, analog signals often change continuously while an analog-to-digital converter (ADC) needs a stable input during conversion. A sample-and-hold (S/H) circuit is widely used to bridge this gap by sampling the signal at a specific time and holding that value steady long enough for accurate conversion. Given Data / Assumptions: The S/H includes a low-resistance switch, a storage capacitor, and a buffer amplifier. The ADC requires a near-constant input during its conversion time. Leakage currents and droop are small but non-zero; hold time is chosen so droop error remains within an LSB. Signals can be time-varying (audio, sensors, control feedback). Concept / Approach:The S/H operates in two modes: sample (track) and hold. In sample mode, the capacitor quickly charges to the instantaneous input level. In hold mode, the switch opens; the buffer presents high input impedance to minimize capacitor discharge so the voltage remains substantially constant during the ADC’s conversion interval. Step-by-Step Solution: Identify need: ADC conversion requires stable input to avoid conversion error from slewing.Use S/H to capture the signal at the desired instant (acquisition time must be short enough).Switch to hold: preserve the captured voltage while the ADC converts.Ensure hold droop and aperture uncertainty remain below the allowed error budget (typically < 0.5 LSB). Verification / Alternative check:Compare conversions with/without S/H on a fast-changing input. Without S/H, codes vary due to input motion; with S/H, codes stabilize and track the chosen sampling instant, validating the role of the S/H stage. Why Other Options Are Wrong: Incorrect: contradicts standard data-acquisition practice.Applies only under ideal, zero-leakage conditions: practical S/Hs are designed so non-idealities are within spec; the statement remains correct.Not applicable to ADC-based systems: S/H is specifically used with ADCs, especially SAR and pipeline types. Common Pitfalls:Underestimating acquisition time; ignoring droop during long conversions; neglecting buffer bandwidth so the capacitor cannot charge fully; forgetting aperture jitter limits for high-frequency inputs. Final Answer:Correct

Question 18

DAC specifications: Is the relative accuracy (static linearity) of a digital-to-analog converter determined by its settling time specification?

Accepted Answer

Introduction / Context:Digital-to-analog converters (DACs) have static and dynamic performance metrics. This question distinguishes relative accuracy (a static linearity measure) from settling time (a dynamic time-domain measure), preventing confusion when reading datasheets or selecting parts. Given Data / Assumptions: Relative accuracy is commonly specified as integral nonlinearity (INL) in LSBs. Settling time is the time for output to enter and remain within a specified error band after a code step. Different DAC architectures exhibit different dynamic behavior, but static linearity definitions are universal. Concept / Approach:Relative accuracy (linearity) quantifies how closely the DAC’s transfer function matches an ideal straight line across the full code range. Settling time addresses how fast the DAC output approaches its final value after a step. These are orthogonal characteristics: a DAC can be very linear (good relative accuracy) yet slow to settle, or fast-settling but with poor linearity. Step-by-Step Solution: Define relative accuracy: maximum INL deviation from ideal in LSBs.Define settling time: time to be within, for example, ±0.5 LSB of final value after a step.Compare: one is static transfer accuracy; the other is temporal response speed.Conclude the statement tying relative accuracy to settling time is incorrect. Verification / Alternative check:Check any DAC datasheet: INL/DNL (static) appear in the accuracy section; settling time in the dynamic characteristics section. Values change with architecture and load independently, confirming the separation. Why Other Options Are Wrong: Correct / architecture qualifiers: Regardless of architecture or S/H usage, relative accuracy is not defined by settling time. Common Pitfalls:Equating “within ±0.5 LSB after t” to overall accuracy; ignoring thermal drift and reference accuracy; assuming faster is always more accurate. Final Answer:Incorrect

Question 19

DAC resolution concept: One way to compute resolution is to take the ratio of one LSB step size to the full-scale output range of the digital-to-analog converter.

Accepted Answer

Introduction / Context:Resolution quantifies the smallest change a DAC can produce in its output. Expressing resolution as a ratio links the LSB step to full-scale, helping designers relate code width to analog precision in percent or parts per million (ppm). Given Data / Assumptions: n-bit DAC with full-scale range FS (voltage or current). One LSB step size = FS / (2^n − 1) or FS / 2^n depending on convention; ratio form remains consistent. Reference and scaling networks are ideal for the definition. Concept / Approach:Resolution can be stated as a fraction or percentage: LSB_step / FS. For a mid-tread DAC using FS_ref and 2^n codes, the step is approximately FS / 2^n. Thus resolution ≈ 1 / 2^n in normalized units, or 100% / 2^n as a percentage. This complements stating resolution directly as the LSB size in volts or amperes. Step-by-Step Solution: Define FS and n.Compute step size: step = FS / 2^n (approximation widely used).Form the ratio: resolution = step / FS ≈ 1 / 2^n.Express as % or ppm to compare across systems. Verification / Alternative check:For n = 8 and FS = 5 V, step ≈ 5 / 256 = 19.53 mV, ratio = 19.53 mV / 5 V ≈ 0.0078125 = 0.78125% = 1 / 128, consistent with 1 / 2^n when using the 0-to-FS idealization. Why Other Options Are Wrong: Incorrect: contradicts standard definitions used in textbooks and datasheets.Only valid for voltage-output or 5 V reference: the ratio definition is architecture-agnostic; it applies equally to current DACs and any FS value. Common Pitfalls:Confusing resolution with accuracy; mixing FS of the code range with the reference tolerance; ignoring gain/offset errors that do not change resolution. Final Answer:Correct

Question 20

Flash ADC principle: In a flash (parallel) analog-to-digital converter, an array of comparators simultaneously compares ladder-generated reference levels to the analog input voltage.

Accepted Answer

Introduction / Context:Different ADC architectures trade speed, complexity, and power. Flash ADCs are the fastest because they perform all necessary comparisons at once. Understanding how they use comparator arrays clarifies why they achieve nanosecond-class conversion times. Given Data / Assumptions: Reference ladder (resistive) generates evenly spaced thresholds. Comparator array compares VIN to each threshold simultaneously. Thermometer code from comparators is encoded to binary at the output. No sequencing or iterative search is required during conversion. Concept / Approach:For an n-bit flash ADC, 2^n − 1 comparators are used. Each comparator outputs HIGH if VIN exceeds its threshold. The collection of outputs forms a thermometer code whose number of HIGHs corresponds to the quantized level; a priority or thermometer-to-binary encoder then produces the digital code. This parallelism is the source of the flash architecture’s speed advantage. Step-by-Step Solution: Apply VIN to all comparator positive inputs simultaneously.Feed reference ladder nodes to the comparator negative inputs.Read the comparator vector (thermometer code).Encode to binary to obtain the final digital output. Verification / Alternative check:Examine timing: conversion occurs within one comparator decision time plus encoder latency—no per-bit cycles—confirming parallel operation. Why Other Options Are Wrong: Incorrect / SAR statements: SAR uses a DAC and a single comparator over multiple clocked steps, not a full comparator array.Clock requirement: flash conversion itself does not require a conversion clock; it is inherently combinational. Common Pitfalls:Underestimating power and input capacitance of large comparator arrays; ignoring bubble errors and the need for bubble correction in the encoder. Final Answer:Correct

Analog and Digital Converters Questions

Questions

Practice smarter