Flash ADC trade-off What is the primary disadvantage of a flash (parallel) analog-to-digital converter architecture?
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Ait requires the input voltage to be applied to the inputs simultaneously
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Ba long conversion time is required
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Ca large number of output lines is required to simultaneously decode the input voltage
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Da large number of comparators is required to represent a reasonable sized binary number
Answer
Correct Answer: a large number of comparators is required to represent a reasonable sized binary number
Explanation
Introduction / Context:Flash ADCs are the fastest ADC topology, used in high-speed data acquisition and RF front ends. However, their speed comes with a key cost.
Given Data / Assumptions:
- N-bit flash ADC uses 2^N − 1 comparators.
- Resistor ladder and thermometer-to-binary encoder are part of the design.
Concept / Approach:The parallel comparison of the input against all thresholds simultaneously yields near-instant conversion, but the hardware scales exponentially with resolution, making higher-bit flash ADCs area- and power-intensive.
Step-by-Step Solution:State comparator count: for N bits, need 2^N − 1 comparators.Implication: doubling resolution by 1 bit nearly doubles the comparator count.Conclusion: the large comparator requirement is the primary disadvantage.
Verification / Alternative check:Example: 8-bit flash → 255 comparators; 10-bit → 1023 comparators.
Why Other Options Are Wrong:Long conversion time: false; flash is the fastest.Input applied simultaneously and output lines: not the core limiting disadvantage compared to comparator count.
Common Pitfalls:Confusing flash with successive-approximation or integrating ADCs, which trade speed for hardware complexity.
Final Answer:a large number of comparators is required to represent a reasonable sized binary number