Flash ADC principle: In a flash (parallel) analog-to-digital converter, an array of comparators simultaneously compares ladder-generated reference levels to the analog input voltage.

Introduction / Context:
Different ADC architectures trade speed, complexity, and power. Flash ADCs are the fastest because they perform all necessary comparisons at once. Understanding how they use comparator arrays clarifies why they achieve nanosecond-class conversion times.

Given Data / Assumptions:

• Reference ladder (resistive) generates evenly spaced thresholds.
• Comparator array compares VIN to each threshold simultaneously.
• Thermometer code from comparators is encoded to binary at the output.
• No sequencing or iterative search is required during conversion.

Concept / Approach:
For an n-bit flash ADC, 2^n − 1 comparators are used. Each comparator outputs HIGH if VIN exceeds its threshold. The collection of outputs forms a thermometer code whose number of HIGHs corresponds to the quantized level; a priority or thermometer-to-binary encoder then produces the digital code. This parallelism is the source of the flash architecture’s speed advantage.

Step-by-Step Solution:

Verification / Alternative check:
Examine timing: conversion occurs within one comparator decision time plus encoder latency—no per-bit cycles—confirming parallel operation.

Why Other Options Are Wrong:

Common Pitfalls:
Underestimating power and input capacitance of large comparator arrays; ignoring bubble errors and the need for bubble correction in the encoder.

Final Answer:
Correct