Question 1

Numeric resolution claim: “An 8-bit digital-to-analog converter has a resolution of 0.125 V.” Evaluate this claim.

Accepted Answer

Introduction / Context: Stating a specific resolution in volts for a DAC without specifying full-scale (FS) is incomplete. Resolution in volts depends on both bit depth and the FS range (reference). This question highlights the necessity of including FS when quoting absolute resolution numbers. Given Data / Assumptions: n = 8 bits (256 codes). Resolution (LSB size) ≈ FS / 2^n for typical definitions. FS is not given; therefore a unique voltage value cannot be asserted. Concept / Approach: Absolute resolution in volts is proportional to FS. For an 8-bit DAC, LSB ≈ FS / 256. If FS = 5 V, LSB ≈ 19.53 mV; if FS = 10 V, LSB ≈ 39.06 mV; if FS = 32 V, LSB = 0.125 V. Thus, the value 0.125 V is not universally true—it corresponds to a particular FS, not 8 bits alone. Step-by-Step Solution: Identify missing parameter: FS not specified.Write general formula: LSB ≈ FS / 2^n.Plug cases: For 8 bits, LSB values vary linearly with FS.Conclude the universal claim is incorrect. Verification / Alternative check: Given 0.125 V, back-solve FS ≈ 0.125 * 256 = 32 V. The statement would be conditionally correct only if FS is known to be 32 V, which the stem does not specify. Why Other Options Are Wrong: Correct: false because FS is unspecified.Correct only if full-scale equals 32 V: a useful conditional note, but the stem claims universality; hence the correct classification is “Incorrect.”Current-output qualifier: architecture does not fix the numeric LSB without FS. Common Pitfalls: Quoting “mV per LSB” without FS context; mixing nominal reference with buffered full-scale; ignoring gain settings that scale FS. Final Answer: Incorrect

Question 2

Bit depth vs. accuracy: If we increase bit width from 4 bits to 8 bits, does the conversion accuracy merely double?

Accepted Answer

Introduction / Context: Bit depth strongly affects resolution and potential accuracy in digital-to-analog conversion. This item tests intuition: moving from 4 to 8 bits increases code levels from 16 to 256, which is far more than a mere doubling of precision. Given Data / Assumptions: Resolution (normalized) ≈ 1 / 2^n. 4-bit → 1/16; 8-bit → 1/256. “Relative accuracy” here refers to ideal quantization resolution absent nonidealities. Concept / Approach: Doubling the number of bits increases resolution exponentially: each added bit halves the LSB size. Going from 4 to 8 bits adds 4 bits, yielding a 2^4 = 16× improvement, not 2×. Therefore, the statement that accuracy “doubles” is incorrect by an order of magnitude for ideal quantization limits. Step-by-Step Solution: Compute levels: 4-bit → 16 codes; 8-bit → 256 codes.Compute normalized resolution: 1/16 vs. 1/256.Compare: improvement factor = (1/16) / (1/256) = 16.Conclude the claim of only doubling is false. Verification / Alternative check: Quantization noise power scales with LSB^2; adding 4 bits reduces quantization noise by 24 dB (approximately 6.02 dB/bit), far more than a 6 dB “doubling.” Why Other Options Are Wrong: Correct or conditional options: accuracy improvement is 16× ideally, not 2×; monotonicity and reference ideality do not change the exponential relation of bits to resolution. Common Pitfalls: Confusing absolute accuracy (affected by INL/DNL, reference tolerance) with bit-limited resolution; assuming linear rather than exponential scaling with additional bits. Final Answer: Incorrect

Question 3

Monotonicity definition: A DAC is called nonmonotonic if its output magnitude increases for every increasing input code. Classify this statement.

Accepted Answer

Introduction / Context: Monotonicity is critical in control and instrumentation: as the input code steps up, the analog output should never step down. Misstating the definition leads to misinterpretation of datasheets and system stability issues. Given Data / Assumptions: Monotonic DAC: output does not decrease when input code increases by one step. Nonmonotonic DAC: at some code transition, output decreases (step reversal). Architecture (R-2R, current steering, segmented) does not change the definition. Concept / Approach: The statement provided actually defines monotonic behavior, not nonmonotonic. A nonmonotonic DAC can create control loop oscillations or dead zones because increased command produces a lower output near certain transitions—an unacceptable condition for many applications. Step-by-Step Solution: Recall correct definition of monotonicity: nondecreasing output for increasing input code.Identify contradiction: the claim equates that behavior with “nonmonotonic.”Conclude classification: the statement is incorrect.Note: Nonmonotonicity is often linked to DNL errors > 1 LSB. Verification / Alternative check: Check DNL: if worst-case DNL ≤ 1 LSB, the DAC is guaranteed monotonic. If DNL exceeds 1 LSB, nonmonotonic steps can occur, confirming the industry usage of the term. Why Other Options Are Wrong: Correct/architecture qualifiers: Monotonicity definitions are universal, independent of coding scheme or architecture. Common Pitfalls: Confusing monotonicity with linearity; assuming glitch energy implies nonmonotonicity (glitches are transient, not static step order errors). Final Answer: Incorrect

Question 4

Name the device: A(n) ________ converts an analog input quantity into a digital output code suitable for processing or storage.

Accepted Answer

Introduction / Context: Signal chains often begin with sensors producing analog voltages or currents. To process these signals in digital systems, a device is needed to translate analog values into binary codes: the analog-to-digital converter (ADC). Given Data / Assumptions: Input is an analog quantity (voltage/current). Output must be a digital code (binary or two’s complement). No specific architecture is mandated by the question. Concept / Approach: An ADC samples (implicitly or explicitly) an analog input and assigns it to one of many discrete quantization levels, outputting a corresponding digital code. Many architectures exist—flash, SAR, sigma-delta, pipeline—and all meet the functional definition. “Flash converter” is a subtype of ADC; “DAC” performs the inverse function; “bipolar converter” is not a standard device class name in this context. Step-by-Step Solution: Identify the functional requirement: analog in → digital out.Map requirement to device class: analog-to-digital converter.Recognize flash as a specific ADC type, not the general answer.Exclude DAC (reverse direction). Verification / Alternative check: Any ADC datasheet demonstrates analog input pins, sampling front-end, reference, and a digital output interface (parallel, SPI, I2C), confirming the function. Why Other Options Are Wrong: bipolar converter: ambiguous term; not the standard device name.flash converter: correct subtype but less general than “ADC.”DAC: performs digital → analog, opposite of what is asked. Common Pitfalls: Confusing the general class (ADC) with a specific architecture; overlooking required sampling/hold behavior in faster ADCs. Final Answer: ADC

Question 5

Definition check: The property that one binary step change at a DAC input should yield exactly one output step, without reversals or missing codes, is called ________.

Accepted Answer

Introduction / Context: Among DAC specifications, monotonicity is crucial for control applications and smooth waveform generation. It guarantees that as the input code increments by one, the output never decreases and advances by one quantization step at a time without inversions. Given Data / Assumptions: Discrete output levels separated by the LSB step. Input codes change in single-step increments. No transient behavior (glitch impulse) considered in the static definition. Concept / Approach: Monotonicity means nondecreasing static transfer function versus input code. It prevents step reversals that could destabilize feedback systems. While resolution defines the size of steps, linearity (INL/DNL) measures closeness to an ideal line and step uniformity; accuracy aggregates gain/offset/linearity against absolute references. The term that matches the “one step in → one step out” behavior is monotonicity (often tied to DNL ≤ 1 LSB). Step-by-Step Solution: Identify required behavior: no step reversals or missing codes on single-code increments.Map to spec: this is monotonicity (static property).Differentiate from resolution (step size magnitude) and linearity (shape error).Select the correct term: monotonicity. Verification / Alternative check: Datasheets often state “Guaranteed monotonic to n bits” which ensures no reversals; this aligns with the described behavior. Why Other Options Are Wrong: linearity: concerns deviation from a straight line, not strictly step order.accuracy: umbrella term including gain/offset/INL; not specific to step behavior.resolution: LSB size, not step order correctness. Common Pitfalls: Equating missing codes with nonmonotonicity (related but distinct); ignoring that good DNL typically guarantees monotonicity. Final Answer: monotonicity

Question 6

Clocking requirement: Which ADC architecture typically requires no conversion clock because timing or iterative sequencing is unnecessary?

Accepted Answer

Introduction / Context: ADC architectures vary in whether they need a conversion clock. Some rely on iterative or oversampling sequences driven by clocks, while others operate combinationally. Understanding these differences helps in system timing design and clock-domain planning. Given Data / Assumptions: Flash ADCs perform all comparisons in parallel via comparator arrays. SAR and dual-slope ADCs require sequencing and thus a clock. “Bipolar” is not an ADC architecture; “actuator” is not an ADC at all. Concept / Approach: Flash ADCs use a resistor ladder to create many reference thresholds and simultaneously compare the input to all thresholds. The resulting thermometer code is encoded to binary. Because there is no step-by-step search or integration period, a conversion clock is not required for the conversion itself (though clocks may be used for output latching or system interfacing). Step-by-Step Solution: Identify architectures: flash (parallel), SAR (binary search), dual-slope (integrating), sigma-delta (oversampling).Determine which needs no iterative timing: flash operates in one parallel decision.Exclude others: SAR and dual-slope inherently require clocked sequencing.Choose “Flash” as the correct answer. Verification / Alternative check: Review timing diagrams: SAR shows multiple comparison cycles per sample; dual-slope shows integrate and deintegrate phases. Flash shows a static comparison path with optional latch timing only. Why Other Options Are Wrong: Dual: shorthand for dual-slope integrating ADCs; requires precise clocking.Bipolar: not an ADC architecture name; sometimes refers to input polarity handling.Actuator: not an ADC at all. Common Pitfalls: Confusing the presence of output latches or interface clocks with the conversion mechanism; assuming “fast” always means “clocked.” Final Answer: Flash

Question 7

Digital-to-Analog Converters (DACs): The practical issues with a binary-weighted resistor DAC (large resistor ratio spread, switch accuracy, and sensitivity to tolerances) can be overcome by using which alternative architecture?

Accepted Answer

Introduction / Context: Digital-to-analog converters transform binary input words into proportional analog voltages or currents. A common entry-level topology is the binary-weighted resistor DAC, but it suffers from component-ratio and switching challenges as resolution grows. This question asks which DAC architecture addresses those pain points most directly. Given Data / Assumptions: Target: overcome problems of binary-weighted resistor DACs. Typical problems include wide resistor value spread (1R, 2R, 4R, …), tight tolerance needs, and switch on-resistance errors. We assume mainstream voltage-output DAC implementations. Concept / Approach: The R/2R ladder DAC replaces the exponential resistor set with only two resistor values: R and 2R. This uniformity improves matching, reduces sensitivity to absolute tolerance (relying more on ratio matching), and eases layout. It also simplifies switch drive because each bit sees the same impedance environment. Step-by-Step Solution: Identify core limitation: binary-weighted requires precise values like R, 2R, 4R, … up to 2^(n-1)R.Recognize effect: higher n means extreme ratios and mismatch risk.Select architecture that uses only two values → R/2R ladder.Conclude that an R/2R ladder is the best-fit remedy. Verification / Alternative check: Compare INL/DNL sensitivity: for the same process, R/2R ladders exhibit better monotonicity and yield because they depend on resistor ratio matching rather than absolute value precision. Why Other Options Are Wrong: an 8-bit binary-weighted resistor DAC: retains the same structural issues; it merely fixes resolution at 8 bits. a staircase DAC: vague term, generally refers to the DAC output, not a topology that solves matching. a flash DAC: very fast ADC type; not a DAC architecture that addresses resistor weighting problems. Common Pitfalls: Assuming “more bits” or “different code” removes mismatch problems; architecture, not just resolution, determines sensitivity. Final Answer: an R/2R ladder DAC

Question 8

Practical resolution limit of a binary-weighted resistor DAC: up to how many bits is this approach generally feasible before resistor ratio spread becomes impractical?

Accepted Answer

Introduction / Context: Binary-weighted resistor DACs require resistor values in powers of two. As resolution increases, the ratio between the smallest and largest resistors grows quickly, stressing tolerance, temperature tracking, and switch on-resistance requirements. This item asks for the commonly cited practical upper limit in bits. Given Data / Assumptions: Binary-weighted topology (R, 2R, 4R ... 2^(n-1)R). General-purpose, discrete or monolithic resistors with realistic tolerances. Focus on practical, economical implementation rather than extreme custom trimming. Concept / Approach: The resistor spread grows exponentially with resolution. For 8 bits, the largest element is 128R relative to the least significant bit branch. Beyond around 8 bits, achieving low integral and differential nonlinearity with untrimmed parts becomes hard and expensive. Hence designers typically shift to R/2R ladders for higher resolution. Step-by-Step Solution: Relate resolution to resistor spread: n bits → largest branch is 2^(n-1)R.Check feasibility: matching, temperature coefficients, and switch errors accumulate with spread.Industry practice: about 8 bits is a common, practical ceiling without heavy trimming.Therefore the best choice is 8 bits. Verification / Alternative check: Reference application notes consistently recommend R/2R ladders at or above 8 bits due to manufacturability and linearity advantages. Why Other Options Are Wrong: 10 bits: possible only with tight trims, special processes; not generally practical. 2 bits / 4 bits: these are trivial and not a “limit.” Common Pitfalls: Confusing absolute tolerance with ratio matching; the main issue is exponential spread across branches, not just nominal value accuracy. Final Answer: 8 bits

Question 9

Root causes of inaccurate analog-to-digital conversion: select the most appropriate source of conversion error from the choices given.

Accepted Answer

Introduction / Context: Accurate analog-to-digital conversion depends on stable sampling, quantization logic, and timing. Many systems employ a sample-and-hold (S/H) circuit to freeze the input during conversion so the ADC sees a constant value. If the S/H misbehaves, conversion accuracy collapses. Given Data / Assumptions: An ADC requires a stable input during its conversion interval. A sample-and-hold is commonly used to maintain that stability. We aim to identify the most direct and likely cause of conversion inaccuracy. Concept / Approach: A faulty S/H introduces droop, feedthrough, or aperture jitter errors. Droop changes the held value during conversion; feedthrough injects switching artifacts; aperture jitter changes the effective sampling instant. These directly corrupt the digital output code. Other listed factors are either neutral or less direct under typical operation. Step-by-Step Solution: Consider each option for direct impact on accuracy.Identify S/H faults as the most immediate source of conversion error.Link mechanisms: droop and jitter alter the effective analog value at conversion time.Select “faulty sample-and-hold circuitry.” Verification / Alternative check: Datasheets specify S/H droop rate, aperture jitter, and hold step precisely because they dominate precision ADC error budgets in many applications. Why Other Options Are Wrong: constant analog input voltage: a stable input is beneficial, not harmful. linear ramp usage: common in certain converters; not inherently inaccurate. intermittent counter inputs: may affect a specific ADC architecture’s timing, but not a universal dominant error like S/H faults. Common Pitfalls: Underestimating the importance of S/H quality; ignoring layout and reference stability which also matter but are not options here. Final Answer: faulty sample-and-hold circuitry

Question 10

ADC conversion time behavior: which ADC type has a fixed conversion time that does not depend on the analog input value?

Accepted Answer

Introduction / Context: Different analog-to-digital converter (ADC) architectures exhibit different timing behaviors. Some have conversion times that vary with the input, while others are constant. Selecting the right architecture often hinges on this property. Given Data / Assumptions: Focus is the dependence (or independence) of conversion time on input level. Standard ADC architectures: successive approximation, dual-slope, flash, etc. We assume typical single-shot conversions. Concept / Approach: Successive approximation (SAR) ADCs perform a fixed number of comparison steps equal to the resolution in bits, so conversion time is essentially constant and independent of input value. Dual-slope converters integrate over a fixed period but are not presented correctly here as “Dual”; their timing is fixed but used primarily for noise rejection and precision—however, the best match to the phrasing and common exam focus is SAR. “Recessive approximation” is not a standard term. Step-by-Step Solution: Map architectures to timing: SAR → fixed N steps; dual-slope → fixed integration windows; flash → very fast constant time.Given the options and common curricula, SAR is the canonical answer for fixed, input-independent timing.Select “Successive approximation.”Note that “Substandard/Recessive” are distractors. Verification / Alternative check: Typical SAR datasheets specify t_conv as a constant number of clock cycles, independent of input amplitude. Why Other Options Are Wrong: Substandard: not an architecture. Dual: ambiguous wording; dual-slope exists but is not the expected answer here. Recessive approximation: not a valid term. Common Pitfalls: Confusing architecture names; assuming conversion time variability is dominated by input amplitude in SAR (it is not). Final Answer: Successive approximation

Question 11

Terminology in DAC specifications: the number of binary input bits that a DAC accepts is referred to as its ________.

Accepted Answer

Introduction / Context: Digital-to-analog converter datasheets contain several common terms: resolution, accuracy, linearity, and monotonicity. Distinguishing these concepts is foundational for selecting and applying DACs. Given Data / Assumptions: The DAC accepts an N-bit digital input word. We are naming the parameter that counts those bits. Definitions follow standard instrumentation terminology. Concept / Approach: Resolution is the smallest step size the converter can produce, typically 1 LSB = full-scale range / 2^N, where N is the number of input bits. Accuracy describes how close the actual analog output is to the ideal value. Linearity (INL/DNL) measures deviation from an ideal straight transfer curve. Monotonicity means each code step never decreases output value. Step-by-Step Solution: Identify the asked quantity: number of binary bits at the input.Match definition: “resolution” is N bits and determines LSB size.Therefore choose “resolution.”Reinforce: more bits → finer steps. Verification / Alternative check: Datasheet tables list “Resolution: N bits” separately from accuracy specs, confirming the terminology. Why Other Options Are Wrong: accuracy: depends on gain/offset and linearity errors, not just bit count. linearity: relates to code-to-output straightness. monotonicity: property of always increasing with code; not a count of bits. Common Pitfalls: Equating bit count with accuracy; a high-resolution DAC can still be inaccurate if calibration is poor. Final Answer: resolution

Analog and Digital Converters Questions