Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:Two common DAC topologies are binary-weighted resistor DACs and R–2R ladder DACs. In a binary-weighted DAC, each input bit contributes an analog current or voltage weighted in proportion to its binary significance (MSB contributes twice that of the next, and so on). The resistor network must therefore be sized to implement these binary weights.
Given Data / Assumptions:
Concept / Approach:For binary weighting, the contribution of bit k is proportional to 2^k relative to the LSB. Using resistors, this is achieved by setting their values inversely proportional to the desired current: I = V / R. Thus, to double the weight, halve the resistance. Typical networks choose R, R/2, R/4, ... for MSB→LSB (or the reciprocal, depending on orientation). This directly encodes the binary weights into the resistor values.
Step-by-Step Solution:
Define target weighting: MSB contributes 1/2 of full-scale, next 1/4, etc.Translate to resistor values: choose R_MSB, R_MSB2, R_MSB4, ... so currents scale 1, 1/2, 1/4, ...Connect to summing amplifier or reference node to produce V_out proportional to the code.Hence, resistors are proportional to the binary weights (inversely for current mode).Verification / Alternative check:Contrast with R–2R: that topology uses only two resistor values (R and 2R), avoiding wide tolerance spread; binary-weighted explicitly scales resistors by powers of two.
Why Other Options Are Wrong:
Incorrect: contradicts the defining characteristic of binary-weighted DACs.True only for R–2R: opposite—R–2R does not require proportional resistor scaling.Indeterminate: reference level affects scale, not the proportionality requirement.Common Pitfalls:Assuming R–2R behavior applies to binary-weighted DACs; mixing up voltage-mode and current-mode implementations.
Final Answer:Correct
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