Flash ADC architecture: In a flash (parallel) analog-to-digital converter, the outputs of the bank of comparators feed which digital block to produce the encoded binary word?

Introduction / Context:Flash ADCs are the fastest ADC architecture, using 2^N − 1 comparators to instantly compare the input against a ladder of reference levels. Understanding how these thermometer-coded outputs become binary is key to grasping flash operation.

Given Data / Assumptions:

• Each comparator outputs HIGH if Vin > Vref(threshold).
• Outputs form a thermometer code (a string of 1s followed by 0s).
• We need a digital block to convert thermometer to binary.

Concept / Approach:A priority encoder identifies the highest-order active comparator (the transition from 1s to 0s) and outputs the corresponding binary code. Additional bubble-correction logic may be used to handle metastability or noise.

Step-by-Step Solution:Thermometer pattern arises at comparator outputs.Priority encoder maps the position of the last 1 to a binary word.Optional error correction cleans spurious bubbles for robust coding.Binary code is latched and presented as ADC output.

Verification / Alternative check:Block diagrams of flash ADCs universally show a resistor ladder, comparators, and a priority encoder stage.

Why Other Options Are Wrong:A decoder goes the other direction (binary to one-hot).

Multiplexers and demultiplexers select routes, not encode thermometer codes.

Shift registers serialize/temporize data, not encode it.

Common Pitfalls:Ignoring input bandwidth and comparator kickback; layout and reference ladder integrity are crucial at high speeds.

Final Answer:priority encoder