Active-HIGH S–R latch truth conditions In an active-HIGH input S–R latch (set–reset latch using positive logic), under which input condition does an INVALID state occur?

Introduction / Context:
The set–reset (S–R) latch is the most fundamental memory element in digital electronics. With active-HIGH inputs, asserting S requests Q = 1 (set), and asserting R requests Q = 0 (reset). Understanding which input combinations are allowed and which are forbidden is crucial for reliable design, hazard avoidance, and debug of sequential circuits.

Given Data / Assumptions:

• Latch uses active-HIGH inputs S and R (positive logic).
• Outputs are Q and Q_bar, ideally complementary.
• We seek the condition that produces an invalid or indeterminate state.

Concept / Approach:

In an active-HIGH S–R latch, the truth behavior is: S = 1, R = 0 → set (Q = 1); S = 0, R = 1 → reset (Q = 0); S = 0, R = 0 → hold last state; S = 1, R = 1 → invalid/forbidden because both cross-coupled gates are driven to assert their outputs simultaneously, breaking the complement relationship and risking metastability when released.

Step-by-Step Solution:

Verification / Alternative check:

Analyze cross-coupled NOR implementation (common for active-HIGH): when both inputs = 1, both NOR outputs tend to 0. Releasing to 0,0 can leave the latch in an unpredictable state depending on tiny timing differences, demonstrating the forbidden nature.

Why Other Options Are Wrong:

Both LOW: this is the normal memory/hold condition.

S = 0, R = 1: valid reset request.

S = 1, R = 0: valid set request.

Common Pitfalls:

Confusing active-HIGH with active-LOW conventions; forgetting that the invalid combination is the simultaneous assertion of both control inputs; assuming the latch will always recover to a known state after (1,1) is released—it may not.

Final Answer:

HIGHs are applied simultaneously to both inputs S and R