7475 (transparent latch) vs. 7474 (edge-triggered D flip-flop) What is the key difference between the 7475's enable input and the 7474's clock input?

Introduction / Context:
Different sequential devices capture data under different timing rules. The 7475 is a pair of level-sensitive (transparent) latches, while the 7474 is a pair of edge-triggered D flip-flops. Designers must understand whether data passes through continuously while an enable is asserted or whether it is sampled only on a specific clock edge to avoid hazards and race conditions.

Given Data / Assumptions:

• Part 7475: transparent latch with an enable (often active HIGH).
• Part 7474: D flip-flop with a clock (typically edge-triggered, positive edge in the standard part).
• We compare sensitivity to level vs. edge.

Concept / Approach:

A transparent latch (7475) passes D to Q while the enable level is active; when the enable is inactive, the output holds the last value. An edge-triggered flip-flop (7474) samples D only at a transition (rising edge for positive-edge-triggered) of the clock, holding the sampled value thereafter, regardless of D changes until the next edge.

Step-by-Step Solution:

Verification / Alternative check:

Examine timing diagrams: with a changing D while enable is HIGH, 7475 Q follows; for 7474, Q changes only at the clock edge and ignores mid-cycle D variation.

Why Other Options Are Wrong:

7475 edge-triggered: incorrect—this device is level-sensitive.

Enable asynchronous vs clock synchronous: misleading; both participate in synchronous design, but their sensitivities differ (level vs edge).

Both level-sensitive: false for the 7474.

Common Pitfalls:

Using a transparent latch where an edge-triggered FF is needed can create races; conversely, assuming an FF will pass data during the high level of the clock is also wrong.

Final Answer:

The 7474 is edge-triggered.