Active-HIGH S–R latch behavior after removing a reset An active-HIGH S–R latch has S = 0 and R = 1 (reset asserted). When R transitions to 0 while S remains 0, what is the resulting latch state?

Introduction / Context:Latches store one bit of information by feeding outputs back to inputs. With an active-HIGH S–R latch, S requests Q = 1 and R requests Q = 0. Understanding what happens when a momentary assertion is removed is essential for predicting memory behavior and designing glitch-free control signals.

Given Data / Assumptions:

• Initial inputs: S = 0, R = 1 (reset command active).
• Transition: R → 0 while S remains 0.
• Latch is level-sensitive; after inputs return to 0, the latch holds its last state.

Concept / Approach:

Input combinations for active-HIGH S–R latch are: (1,0) set, (0,1) reset, (0,0) hold, (1,1) invalid. The moment R = 1 forces Q = 0 (reset). When R goes back to 0 and S is 0, inputs become (0,0), which is the hold condition. Therefore, the latch remains in the previously established reset state.

Step-by-Step Solution:

Verification / Alternative check:

Cross-coupled NOR realization confirms the above: asserting R drives its NOR output low and the complementary feedback high. Returning to (0,0) leaves the feedback loop stable at the reset condition.

Why Other Options Are Wrong:

SET: would require S = 1 at some point, which did not occur.

clear: ambiguous wording; in common usage it means reset, but the explicit correct term here is RESET.

invalid: only when S = 1 and R = 1 simultaneously.

Common Pitfalls:

Believing that releasing a control input automatically returns the latch to a default; in fact, latches hold the last commanded state when both controls are inactive.

Final Answer:

RESET