Curioustab

Home » Digital Electronics » Flip-Flops

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

SET
RESET
clear
invalid

Correct Answer: RESET

← Previous Question Next Question→

More Questions from Flip-Flops

What is the difference between the enable input of the 7475 and the clock input of the 7474?
What is the significance of the J and K terminals on the J-K flip-flop?
If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
How is a J-K flip-flop made to toggle?
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
How many flip-flops are required to produce a divide-by-128 device?
A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
For an S-R flip-flop to be set or reset, the respective input must be:
A 555 operating as a monostable multivibrator has an R1 of 220 kΩ. Determine C1 for a pulse width of 4 ms.
Which is not a real advantage of HDL?

Discussion & Comments

No comments yet. Be the first to comment!

Join Discussion