A counter-ramp (single-slope) ADC has 8-bit resolution and a 20 kHz clock. What is the maximum (worst-case) conversion time?

Introduction / Context:
In a counter-ramp (single-slope) ADC, conversion time depends on the input amplitude because the counter must count up from zero until the DAC output just exceeds the input. The worst-case time occurs near full-scale. This question checks your ability to relate resolution, clock, and conversion time.

Given Data / Assumptions:

• Resolution n = 8 bits → up to 2^8 steps.
• Clock frequency fclk = 20 kHz → clock period Tclk = 1 / 20000 = 50 µs.
• Worst case requires approximately 2^8 counts (0 to 255) to reach the input.

Concept / Approach:
Worst-case conversion time tmax for counter-ramp ADC is approximately (2^n) * Tclk. Some treatments use (2^n − 1), which is nearly the same at higher n; here both give essentially 12.8 ms with 8 bits.

Step-by-Step Solution:
Compute Tclk = 1 / 20000 = 0.00005 s = 50 µs.Compute 2^8 = 256 steps.tmax ≈ 256 * 50 µs = 12800 µs = 12.8 ms.

Verification / Alternative check:
If using 255 counts: 255 * 50 µs = 12.75 ms, which rounds to 12.8 ms, confirming the chosen option.

Why Other Options Are Wrong:
6.4 ms: corresponds to 128 counts (7 bits), not 8 bits.0.4 ms or 0.05 ms: far too short for 256 counts at 50 µs per count.25.6 ms: would imply 512 counts or slower clock.

Common Pitfalls:
Forgetting to multiply by the full number of counts or miscomputing the clock period. Also confusing counter-ramp (input-dependent time) with SAR (fixed-time) converters.

Final Answer:
12.8 ms