Dual-slope ADCs are popular in digital multimeters. What are two principal advantages of the dual-slope method?

Introduction / Context:
Dual-slope (integrating) ADCs dominate handheld DMMs because of their accuracy and excellent rejection of periodic noise. This question focuses on recognizing the right trade-offs: noise immunity and cost versus speed.

Given Data / Assumptions:

• Integration over fixed intervals averages out noise (e.g., 50/60 Hz).
• Digital result is based on counted time rather than a high-speed comparator race.
• Low component count and simplicity reduce cost.

Concept / Approach:
By integrating the input and then de-integrating with a reference, the converter rejects common line noise and switching spikes averaged across the window. Hardware is simple (op-amp integrator, comparator, counter, clock), leading to economical designs. The main limitation is speed; it is slower than SAR and pipeline converters.

Step-by-Step Solution:
Identify key strengths: noise rejection and inexpensive circuitry.Eliminate options that claim high speed—dual-slope is not fast.Select the option stating “low sensitivity to noise and low cost.”

Verification / Alternative check:
Examine DMM specs: high resolution counts with long integration times; excellent line-frequency rejection but slow sample rates.

Why Other Options Are Wrong:
A and C: Both incorrectly list high speed.B: “High sensitivity to noise” is the opposite of reality.E: A stable clock is required for timing the de-integration.

Common Pitfalls:
Assuming all ADCs pursue speed first. Dual-slope prioritizes accuracy and noise immunity over throughput.

Final Answer:
Low sensitivity to noise and low cost