A 4-bit stairstep-ramp ADC runs at a 100 kHz clock and has a 10 V full-scale input range. What is the maximum achievable sample rate (samples per second)?

Introduction / Context:
Stairstep-ramp (counter-type) ADCs require the counter to step through codes until the internal DAC matches the input. The worst-case conversion time determines the maximum sample rate. This question links clock frequency, resolution, and throughput.

Given Data / Assumptions:

• Resolution n = 4 bits → 2^n = 16 steps maximum per conversion.
• Clock fclk = 100 kHz → period Tclk = 10 µs.
• Each step costs one clock period.

Concept / Approach:
Maximum sample rate is the reciprocal of worst-case conversion time: fs,max ≈ fclk / 2^n for a counter-type ADC. The input range (10 V) affects the DAC scaling but not the timing formula.

Step-by-Step Solution:
Compute steps = 2^4 = 16.Worst-case time = 16 * 10 µs = 160 µs.fs,max = 1 / 160 µs = 6250 samples/second.

Verification / Alternative check:
Using fs,max ≈ fclk / 2^n: 100,000 / 16 = 6,250, matching the detailed calculation.

Why Other Options Are Wrong:
100,000 sps suggests one code per sample; ignores the 16-count search.“Minimum” labels are incorrect because we are asked for maximum throughput.1,250 sps would imply 80 counts per conversion, not 16.

Common Pitfalls:
Forgetting that counter-type ADCs have input-dependent and step-dependent conversion time; using the clock directly as the sample rate is incorrect.

Final Answer:
6,250 samples/second (maximum)